ASAHI KASEI

[AK8411]

MS0457-E-00

2006/05

5

Input Circuit

DC Direct Coupled Mode

A mode to capture a difference between the sampled signal level at the Sample & Hold

circuit and the reference level to be input on VCLP. It is effective when the Pixel signal level

is output at higher than the reference level.

Sample &

Hold

SHD

CIS

CISIN

VCLP

H: Sample

L: Hold

0.1uF

Offset

DAC

Timing

Control

MCLK

TSMP

Fig. 3 in DC Direct Coupled Mode

CDS Mode

A mode to sample feed-through level of CIS signal (CCD type) and data level, and its

difference is captured. In this scheme, thermal noise overlapped with CIS signal and shift of

Clamp level is cancelled out. It is effective when the pixel signal level is output at lower than

the reference level.

Sample &

Hold #1

Sample &

Hold #2

SHR

SHD

SHR

Clamp

Switch

CIS

CISIN

VCLP

H: Sample

L: Hold

H: Sample

L: Hold

H: Close

L: Open

Clamp

Circuit

Offset

DAC

Timing

Control

MCLK

TSMP

VCLP

Fig. 4 in CDS Mode