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AD9512 Datasheet(PDF) 6 Page - Analog Devices |
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AD9512 Datasheet(HTML) 6 Page - Analog Devices |
6 / 48 page AD9512 Rev. A | Page 6 of 48 Parameter Min Typ Max Unit Test Conditions/Comments DELAY ADJUST OUT4; LVDS and CMOS Shortest Delay Range4 35h <5:1> 11111b Zero Scale 0.05 0.36 0.68 ns 36h <5:1> 00000b Full Scale 0.72 1.12 1.51 ns 36h <5:1> 11111b Linearity, DNL 0.5 LSB Linearity, INL 0.8 LSB Longest Delay Range4 35h <5:1> 00000b Zero Scale 0.20 0.57 0.95 ns 36h <5:1> 00000b Full Scale 9.0 10.2 11.6 ns 36h <5:1> 11111b Linearity, DNL 0.3 LSB Linearity, INL 0.6 LSB Delay Variation with Temperature Long Delay Range, 10 ns5 Zero Scale 0.35 ps/°C Full Scale −0.14 ps/°C Short Delay Range, 1 ns5 Zero Scale 0.51 ps/°C Full Scale 0.67 ps/°C 1 The measurements are for CLK1. For CLK2, add approximately 25 ps. 2 This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. 3 This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. 4 Incremental delay; does not include propagation delay. 5 All delays between the zero scale and full scale can be estimated by linear interpolation. |
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