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PIC24FJ128GA106 Datasheet(PDF) 4 Page - Microchip Technology |
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PIC24FJ128GA106 Datasheet(HTML) 4 Page - Microchip Technology |
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4 / 22 page  PIC24FJ256GA110 FAMILY DS80368N-page 4 2008-2013 Microchip Technology Inc. Silicon Errata Issues 1. Module: Core (RAM Operation) If a RAM read is performed on the instruction immediately prior to enabling Doze mode, an extra read event may occur when Doze mode is enabled. This has no effect on most SFRs and on user RAM space. However, this could cause regis- ters which also perform some action on a read (such as auto-incrementing a pointer or removing data from a FIFO buffer) to repeat that action, possibly resulting in lost data or unexpected operation. Work around Avoid reading registers which perform a second- ary action (e.g., UART and SPI FIFO buffers, and the RTCVAL registers) immediately prior to entering Doze mode. If this cannot be avoided, execute a NOP instruction before entering Doze mode. Affected Silicon Revisions 2. Module: Core (BOR) When the on-chip regulator is enabled (ENVREG tied to VDD), a BOR event may spontaneously occur under the following circumstances: •VDD is less than 2.5V, and either: • the internal band gap reference is being used as a reference with the A/D Converter (AD1PCFGH<1> or <0> = 0) or comparators (CMxCON<1:0> = 11); or • the CTMU module is enabled. Work around Limit the following activities to only those times when the on-chip regulator is not in Tracking mode (LVDIF (IFS4<8>) = 0): • enabling the CTMU module; • selecting the internal band gap as a reference for the A/D Converter or the comparators. Affected Silicon Revisions 3. Module: JTAG (Device Programming) The JTAGEN Configuration bit can be pro- grammed to ‘0’ while using the JTAG interface for device programming. This may cause a situation where JTAG programming can lock itself out of being able to program the device. Work around None. Affected Silicon Revisions 4 Module: UART When the UART is operating using two Stop bits (STSEL = 1), it may sample the first Stop bit instead of the second one. If the device being com- municated with is one using one Stop bit in its communications, this may lead to framing errors. Work around None. Affected Silicon Revisions 5. Module: I/O (PORTB) When RB5 is configured as an open-drain output, it remains in a high-impedance state. The settings of LATB5 and TRISB5 have no effect on the pin’s state. Work around If open-drain operation is not required, configure RB5 as a regular I/O (ODCB<5> = 0). If open-drain operation is required, there are two options: • select a different I/O pin for the open-drain function; or • place an external transistor on the pin, and configure the pin as a regular I/O. Affected Silicon Revisions Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (A5). A3 A5 A6 XX X A3 A5 A6 X A3 A5 A6 XX X A3 A5 A6 X A3 A5 A6 X |
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