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PIC24FJ256GA106 Datasheet(PDF) 5 Page - Microchip Technology |
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PIC24FJ256GA106 Datasheet(HTML) 5 Page - Microchip Technology |
5 / 22 page 2008-2013 Microchip Technology Inc. DS80368N-page 5 PIC24FJ256GA110 FAMILY 6. Module: SPIx (Master Mode) In Master mode, both the SPIx Interrupt Flag (SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may become set one-half clock cycle early, instead of on the clock edge. This occurs only under the following circumstances: • Enhanced Buffer mode is disabled (SPIBEN = 0); and • the module is configured for serial data output changes on transition from clock active to clock Idle state (CKE = 1) If the application is using the interrupt flag to deter- mine when data to be transmitted is written to the transmit buffer, the data currently in the buffer may be overwritten. Work around Before writing to the SPIx buffer, check the SCKx pin to determine if the last clock edge has passed. Example 1 (below) demonstrates a method for doing this. In this example, pin RD1 functions as the SPIx clock, SCKx, which is configured as Idle low. Affected Silicon Revisions 7. Module: CTMU When the CTMU module is selected as the trigger source (SYNCSEL<4:0> = 11000), the input capture and/or output compare trigger may not work. Work around Manually trigger the input capture and/or output compare module(s) after a CTMU event is received. Be certain to compensate for any time latency that results from manually triggering the module. Affected Silicon Revisions EXAMPLE 1: CHECKING THE STATE OF SPIxIF AGAINST THE SPIx CLOCK A3 A5 A6 X A3 A5 A6 X while(IFS0bits.SPI1IF == 0){} //wait for the transmission to complete while(PORTDbits.RD1 == 1){} //wait for the last clock to finish SPI1BUF = 0xFF; //write new data to the buffer |
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