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PIC24FJ256GA110 Datasheet(PDF) 9 Page - Microchip Technology |
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PIC24FJ256GA110 Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 22 page  2008-2013 Microchip Technology Inc. DS80368N-page 9 PIC24FJ256GA110 FAMILY 22. Module: Core (Code Protection) When General Segment Code Protection has been enabled (GCP Configuration bit is pro- grammed), applications are unable to write to the first 512 bytes of the program memory space (0000h through 0200h). In applications that may require the interrupt vectors to be changed during run time, such as bootloaders, modifications to the interrupt vector tables will not be possible. Work around Create two new interrupt vector tables, one each for the IVT and AIVT, in an area of program space beyond the affected region. Map the addresses in the old vector tables to the new tables. These new tables can then be modified as needed to the actual addresses of the ISRs. Affected Silicon Revisions 23. Module: SPI/PPS The ALTRP/ASCK1 functionality is not supported by the A3 revision of this part family. Work around None. Affected Silicon Revisions 24. Module: Oscillator (LPRC) The LPRC may not automatically restart following BOR events (i.e., when supply voltage sags to between the BOR and POR thresholds, then returns to above the BOR level). When this hap- pens, systems that use the LPRC clock may not work. This includes the PLL, Two-Speed Start-up, Fail-Safe Clock Monitor and the WDT. Work around For PLL issues: Select a non-PLL Clock mode as the initial start-up mode, using the FNOSC Config- uration bits (CW2<10:8>). After the application has initialized, switch to a PLL Clock mode in software using the NOSC bits (OSCCON<10:8>). Allow 10 microseconds to elapse between application start-up and a software clock switch. For WDT issues: Disable the WDT by programming the FWDTEN bit (CW1<7>). After the application has initialized, enable the WDT in software by setting the SWDTEN bit (RCON<5>). Allow 10 microseconds to elapse between application start-up and setting SWDTEN. Affected Silicon Revisions 25. Module: CTMU (A/D Trigger) The CTMU may not trigger an automatic A/D con- version after the current source is turned off. This happens even when the A/D trigger control bit, CTTRIG (CTMUCON<8>), has been set. Work around Perform a manual A/D conversion by clearing the SAMP bit (AD1CON1<1>) immediately after the CTMU current source has been stopped. Affected Silicon Revisions 26. Module: Output Compare In PWM mode, the output compare module may miss a compare event when the current duty cycle register (OCxRS) value is 0000h (0% duty cycle) and the OCxRS register is updated with a value of 0001h. The compare event is only missed the first time a value of 0001h is written to OCxRS and the PWM output remains low for one PWM period. Subsequent PWM high and low times occur as expected. Work around If the current OCxRS register value is 0000h, avoid writing a value of 0001h to OCxRS. Instead, write a value of 0002h. In this case, however, the duty cycle will be slightly different from the desired value. Affected Silicon Revisions A3 A5 A6 X A3 A5 A6 X A3 A5 A6 X A3 A5 A6 X A3 A5 A6 X |
Similar Part No. - PIC24FJ256GA110 |
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Similar Description - PIC24FJ256GA110 |
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