HMT84GL7MMR4A-G7 datasheet(5/34 Pages) HYNIX

Part #	HMT84GL7MMR4A-G7

Description	DDR3L SDRAM Load Reduced DIMM Based on 4Gb M-die

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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5 / 34 page

Rev. 1.0 / Jan. 2013

5

Pin Descriptions

Pin Name

Description

Num

ber

Pin Name

Description

Num

ber

CK0

Clock Input, positive line

1

Par_In

Parity bit for the Address and Con-

trol bus

1

CK0

Clock Input, negative line

1

Err_Out

Parity error found on the Address

and Control bus

1

CK1

Clock Input, positive line

1

ODT[0]

On Die Termination Inputs

1

CK1

Clock Input, negative line

1

DQ[63:0]

Data Input/Output

64

CKE[1:0]

Clock Enables

2

CB[7:0]

Data check bits Input/Output

8

CKE[3:2],

ODT[1], TEST

Clock Enables

On Die Termination

Memory bus tool (Not Con-

nected and Not Useable on

DIMMs)

2DQS[8:0]

Data strobes

9

RAS

Row Address Strobe

1

DQS[8:0]

Data strobes, negative line

9

CAS

Column Address Strobe

1

DM[8:0]/

DQS[17:9],

TDQS[17:9]

Data Masks / Data strobes,

Termination data strobes

9

WE

Write Enable

1

DQS[17:9],

TDQS[17:9]

Data Masks / Data strobes,

Termination data strobes

9

S[1:0]

Chip Selects

2

EVENT

Reserved for optional hardware

temperature sensing

1

S[3:2], A17,

A16

Chip Selects

Address Inputs

2TEST

Memory bus test tool (Not Con-

nected and Not Usable on DIMMs)

1

A[9:0],A11,

A[15:13]

Address Inputs

14

RESET

Register and SDRAM control pin

1

A10/AP

Address Input/Autoprecharge

1

VDD

Power Supply

22

A12/BC

Address Input/Burst chop

1

VSS

Ground

59

BA[2:0]

SDRAM Bank Addresses

3

VREFDQ

Reference Voltage for DQ

1

SCL

Serial Presence Detect (SPD)

Clock Input

1

VREFCA

Reference Voltage for CA

1

SDA

SPD Data Input/Output

1

VTT

Termination Voltage

4

SA[2:0]

SPD Address Inputs

3

VDDSPD

SPD Power

1

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HMT84GL7MMR4A-G7 Datasheet(PDF) 5 Page - Hynix Semiconductor

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