HMT451U6AFR8C-RD datasheet(11/60 Pages) HYNIX

Part #	HMT451U6AFR8C-RD

Description	DDR3 SDRAM Unbuffered DIMMs Based on 4Gb A-Die

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Manufacturer	HYNIX [Hynix Semiconductor]

Direct Link	http://www.skhynix.com/kor/main.do

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11 / 60 page

Rev. 1.1 / Jul. 2013

11

Functional Block Diagram

2GB, 256Mx64 Module(1Rank of x16)

DQ4

DQ5

DQ6

DQ7

DQ0

DQ1

DQ2

DQ3

I/O 0

I/O 1

I/O 2

I/O 3

D0

DM0

I/O 4

I/O 5

I/O 6

I/O 7

DQ12

DQ13

DQ14

DQ8

DQ9

DQ10

DQ11

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM1

A0–A14

A0–A14: SDRAMs D0–D3

A0

Serial PD

A1

SA0

SA1

SDA

RAS

RAS: SDRAMs D0–D3

CAS

CAS: SDRAMs D0–D3

CKE0

CKE: SDRAMs D0–D3

WE

WE: SDRAMs D0–D3

CS

BA0–BA2

BA0–BA2: SDRAMs D0–D3

DQS0

DQS1

DQ15

I/O 15

VSS

D0–D3

VDD/VDDQ

D0–D3

VREFDQ

Notes:

1. DQ-to-I/O wiring is shown as recom-

mended but may be changed.

2. DQ/DQS/DQS/ODT/DM/CKE/S relation-

ships must be maintained as shown.

3. DQ,DM,DQS,DQS resistors;Refer to asso-

ciated topology diagram.

4. Refer to the appropriate clock wiring

topology under the DIMM wiring details

section of this document.

5. The pair CK1 and CK1# is terminated in

75ohm but is not used on the module.

6. A15 is not routed on the module.

7. For each DRAM, a unique ZQ resistor is

connected to ground.The ZQ resistor is

240ohm+-1%

8. One SPD exists per module.

SCL

WP

SPD

VDDSPD

ODT0

DQS0

DQS1

ODT: SDRAMs D0–D3

S0

CK0

CK: SDRAMs D0–D3

SA2

D0–D3

VREFCA

A2

CK0CK: SDRAMs D0–D3

LDQS

LDM

UDQS

UDM

DQ20

DQ21

DQ22

DQ23

DQ16

DQ17

DQ18

DQ19

I/O 0

I/O 1

I/O 2

I/O 3

D1

DM2

I/O 4

I/O 5

I/O 6

I/O 7

DQ28

DQ29

DQ30

DQ24

DQ25

DQ26

DQ27

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM3

CS

DQS2

DQS3

DQ31

I/O 15

DQS2

DQS3

LDQS

LDM

UDQS

UDM

DQ36

DQ37

DQ38

DQ39

DQ32

DQ33

DQ34

DQ35

I/O 0

I/O 1

I/O 2

I/O 3

D2

DM4

I/O 4

I/O 5

I/O 6

I/O 7

DQ44

DQ45

DQ46

DQ40

DQ41

DQ42

DQ43

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM5

CS

DQS4

DQS5

DQ47

I/O 15

DQS4

DQS5

LDQS

LDM

UDQS

UDM

DQ52

DQ53

DQ54

DQ55

DQ48

DQ49

DQ50

DQ51

I/O 0

I/O 1

I/O 2

I/O 3

D3

DM6

I/O 4

I/O 5

I/O 6

I/O 7

DQ60

DQ61

DQ62

DQ56

DQ57

DQ58

DQ59

I/O 8

I/O 9

I/O 10

I/O 11

I/O 12

I/O 13

I/O 14

DM7

CS

DQS6

DQS7

DQ63

I/O 15

DQS6

DQS7

LDQS

LDM

UDQS

UDM

RESET

RESET:SDRAMs D0-D3

ZQ

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