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XC6VLX130T Datasheet(PDF) 10 Page - IXYS Corporation |
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XC6VLX130T Datasheet(HTML) 10 Page - IXYS Corporation |
10 / 11 page Virtex-6 Family Overview DS150 (v2.4) January 19, 2012 www.xilinx.com Product Specification 10 Revision History The following table shows the revision history for this document: Notice of Disclaimer The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. Date Version Description of Revisions 02/02/09 1.0 Initial Xilinx release. 05/05/09 1.1 Added the FF1156 package for both the XC6VSX315T and XC6VSX475T devices in Table2, page3. Updated the PCI Express design discussion on page 9 to remove the LogiCORE wrapper (<100 LUT) description and clarify 8 lanes at the 5.0 Gb/s data rate. Clerical edits to Global Clock Lines and 10/100/1000 Mb/s Ethernet Controller (2,500 Mb/s Supported) sections. Overall clarifications made in text. 06/24/09 1.2 Added ordering information and FPGA documentation sections. 09/16/09 2.0 Added Virtex-6 HXT family information. Updated number to 26 Mb in Configuration section. 11/06/09 2.1 Clarified distributed RAM features on page 1. Updated CLB slice number for the XC6VHX565T in Table 1. Updated compliance to the PCI Express Base Specification Revision 2.0. Updated Integrated Interface Blocks for PCI Express Designs section with link to documentation. 01/28/10 2.2 In Table 1, there are two Ethernet MACs in the XC6VHX255T. Under Clock Management, page 5, revised the VCO frequency minimum to 600 MHz which also revised the phase-shift timing increment. Updated GTX transceivers operating data rate range to 6.6 Gb/s. Changed GTX PLL input reference clock frequency divider. 03/24/11 2.3 Changed document classification to Preliminary Product Specification from Advance Product Specification. Updated Figure 1. 01/19/12 2.4 Changed document classification to Product Specification from Preliminary Product Specification. Updated Configuration, CLBs, Slices, and LUTs, Low-Power Gigabit Transceivers, and Virtex-6 FPGA Ordering Information (including Figure 1). |
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