Technical Note

BR93L□□-W Series, 93A□□-WM Series, BR93H□□-WC Series

5/40

www.rohm.com

2011.09 - Rev.G

© 2011 ROHM Co., Ltd. All rights reserved.

●Action timing characteristics

(BR93L□□-W, Ta=-40～+85℃, VCC=2.5～5.5V, BR93A□□-WM, Ta=-40～+105℃, VCC=2.5～5.5V)

Parameter

Symbol

2.5V≦VCC≦5.5V

Unit

Min.

Typ.

Max.

SK frequency

-

-

2

MHz

SK “H” time

230

-

-

ns

SK “L” time

230

-

-

ns

CS “L” time

200

-

-

ns

CS setup time

50

-

-

ns

DI setup time

100

-

-

ns

CS hold time

0

-

-

ns

DI hold time

100

-

-

ns

Data “1” output delay time

-

-

200

ns

Data “0” output delay time

-

-

200

ns

Time from CS to output establishment

-

-

150

ns

Time from CS to High-Z

-

-

150

ns

Write cycle time

-

-

5

ms

(BR93L□□-W, Ta=-40～+85℃, VCC=1.8～2.5V)

Parameter

Symbol

1.8V≦VCC≦2.5V

Unit

Min.

Typ.

Max.

SK frequency

-

-

500

kHz

SK “H” time

0.8

-

-

us

SK “L” time

0.8

-

-

us

CS “L” time

1

-

-

us

CS setup time

200

-

-

ns

DI setup time

100

-

-

ns

CS hold time

0

-

-

ns

DI hold time

100

-

-

ns

Data “1” output delay time

-

-

0.7

us

Data “0” output delay time

-

-

0.7

us

Time from CS to output establishment

-

-

0.7

us

Time from CS to High-Z

-

-

200

ns

Write cycle time

-

-

5

ms

●Sync data input / output timing

○Data is taken by DI sync with the rise of SK.

○At read action, data is output from DO in sync with the rise of SK.

○The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input, at the area

DO where CS is “H”, and valid until the next command start bit is input. And, while CS is “L”, DO becomes High-Z.

○After completion of each mode execution, set CS “L” once for internal circuit reset, and execute the following action mode.

Fig.1 Sync data input / output timing

CS

SK

DO(READ)

DI

DO(WRITE)

tCSS

tSKH

tSKL

tCSH

tDIS

tDI H

tPD1

tPD0

tDF

STATUS VALID