Integrated Silicon Solution, Inc. — 1-800-379-4774

1

Rev. N

02/12/2010

Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability

arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any

published information and before placing orders for products.

IS61VPS25672A IS61LPS25672A

IS61VPS51236A IS61LPS51236A

IS61VPS102418A IS61LPS102418A

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth

expansion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

• JEDEC 100-Pin TQFP, 119-ball PBGA, 165-ball

PBGA, and 209-ball (x72) packages

• Lead-free available

DESCRIPTION

The

and IS61LPS/VPS25672A are high-speed, low-power syn-

chronous static RAMs designed to provide burstable, high-

performance memory for communication and networking

applications. The IS61LPS/VPS51236A is organized as

524,288 words by 36 bits, the IS61LPS/VPS102418A is

organized as 1,048,576 words by 18 bits, and the IS61LPS/

VPS25672A is organized as 262,144 words by 72 bits.

Fabricated with

device integrates a 2-bit burst counter, high-speed SRAM

core, and high-drive capability outputs into a single mono-

lithic circuit. All synchronous inputs pass through regis-

ters controlled by a positive-edge-triggered single clock

input.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be one

to four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

The byte write operation is performed by using the byte

write enable (

BWE) input combined with one or more

individual byte write signals (

BWx). In addition, Global

Write (

GW) is available for writing all bytes at one time,

regardless of the byte write controls.

Bursts can be initiated with either

ADSP (Address Status

Processor) or

ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally and controlled by the

ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

256K x 72, 512K x 36, 1024K x 18

18Mb SYNCHRONOUS PIPELINED,

SINGLE CYCLE DESELECT STATIC RAM

MAY 2010

FAST ACCESS TIME

Symbol

Parameter

250

200

Units

Clock Access Time

2.6

3.1

ns

Cycle Time

4

5

ns

Frequency

250

200

MHz