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IS43R16160B-6TLI Datasheet(PDF) 4 Page - Integrated Silicon Solution, Inc |
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IS43R16160B-6TLI Datasheet(HTML) 4 Page - Integrated Silicon Solution, Inc |
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4 / 41 page  4 Integrated Silicon Solution, Inc. Rev. E 08/13/2010 IS43R83200B, IS46R83200B IS43R16160B, IS46R16160B PIN FUNCTION CLK, /CLK Input Clock: CLK and /CLK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CLK and negative edge of /CLK. Output (read) data is referenced to the crossings of CLK and /CLK (both directions of crossing). CKE Input Clock Enable: CKE controls internal clock. When CKE is low, internal clock for the following cycle is ceased. CKE is also used to select auto / self refresh. After self refresh mode is started, CKE becomes asynchronous input. Self refresh is maintained as long as CKE is low. /CS Input Chip Select: When /CS is high, any command means No Operation. /RAS, /CAS, /WE Input Combination of /RAS, /CAS, /WE defines basic commands. A0-12 Input A0-12 specify the Row / Column Address in conjunction with BA0,1. The Row Address is specified by A0-12. The Column Address is specified by A0-9(x8) and A0-8(x16). A10 is also used to indicate precharge option. When A10 is high at a read / write command, an auto precharge is performed. When A10 is high at a precharge command, all banks are precharged. BA0,1 Input DQ0-7 (x8), DQ0-15 (x16), Input / Output DQS (x8) VDD, VDDQ, VDDQ, and VSS Power Supply Power Supply for the memory array and peripheral circuitry. VSSQ Power Supply VSSQ are supplied to the Output Buffers only. Bank Address: BA0,1 specifies one of four banks to which a command is applied. BA0,1 must be set with ACT, PRE, READ, WRITE commands. Data Input/Output: Data bus Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-DQ7; UDQS correspond to the data on DQ8-DQ15 SYMBOL TYPE DESCRIPTION DM (x8) Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-DQ7; UDM corresponds to the data on DQ8-DQ15. Input / Output Vref Input SSTL_2 reference voltage. UDQS, LDQS (x16) UDM, LDM (x16) |
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