＜M　F　T＞

RT8H062E

TIMING DIAGRAM

NOTES

1．The VCC rises up to detective voltage(VsH), then reset is released.

2．OUT terminal(Open collector) generate High signal, after tDOUT time decided from capacity at Delay terminal.

Charge of TC begins.

3．This MFT watch WD signal from when TC rises up from VTCthL to VTCthH. If no signal input WD, OUT terminal generate Low signal.

4．When TC falls to VTCthL, OUT terminal generate High signal.

5．Due to the power failure etc, VCC falls to VsL, OUT terminal generate Low signal.

6．VCC rises up to VsH, OUT terminal generate High signal (if no Cdelay capacity).

7．If normal clock signal is entered in twd time, TC terminal is decharged. And if TC terminal falls to VTCthL, TC begins chaerge.

8．If no signal is entered in twd time, OUT terminal generate Low signal.

9．When VCC falls to VsL, OUT terminal generate Low signal.

*About C terminal

Please connect capacity C terminal-GND terminal always. This capacity is always necessary for detected edge of WD signal

And, for detected abnormal state of WD's high fixation, This capacity can detect normal time of WD's high fixation.

When High signal is entered in WD terminal, twdh[s] or more, TC terminal begins charge, and begin operate 3．.

110805

（ 3 ／ 4 ）

WATCH DOG TIMER

VCC

TC

OUT

WD

1

34

5

6

7

8

9

VsH

VTCthH

VTCthL

VsL

2

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