1

Rev. B

06/03/08

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time

without notice.

ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to

obtain the latest version of this device specification before relying on any published information and before placing orders for products.

IS61WV10248ALL

IS61WV10248BLL

IS64WV10248BLL

1M x 8 HIGH-SPEED CMOS STATIC RAM

JUNE 2008

FEATURES

• High-speed access times:

8, 10, 20 ns

• High-performance, low-power CMOS process

• Multiple center power and ground pins for

greater noise immunity

• Easy memory expansion with

CE and OE

options

•

CE power-down

• Fully static operation: no clock or refresh

required

• TTL compatible inputs and outputs

• Single power supply

speed = 20ns for Vcc = 1.65V to 2.2V

speed = 10ns for Vcc = 2.4V to 3.6V

speed = 8ns for Vcc = 3.3V + 5%

• Packages available:

– 48-ball miniBGA (9mm x 11mm)

– 44-pin TSOP (Type II)

• Industrial and Automotive Temperature Support

• Lead-free available

DESCRIPTION

The

are very high-speed, low power, 1M-word by 8-bit CMOS

static RAM. The IS61WV10248ALL/BLL and

IS64WV10248BLL are fabricated using

performance CMOS technology. This highly reliable

process coupled with innovative circuit design tech-

niques, yields higher performance and low power con-

sumption devices.

When

CE is HIGH (deselected), the device assumes a

standby mode at which the power dissipation can be

reduced down with CMOS input levels.

The IS61WV10248ALL/BLL and IS64WV10248BLL

operate from a single power supply and all inputs are

TTL-compatible.

The IS61WV10248ALL/BLL and IS64WV10248BLL are

available in 48 ball mini BGA and 44-pin TSOP (Type II)

packages.

FUNCTIONAL BLOCK DIAGRAM

A0-A19

CE

OE

WE

1M X 8

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

VDD

I/O

DATA

CIRCUIT

I/O0-I/O7