HEF4053B_13 datasheet(11/20 Pages) NXP

Part #	HEF4053B

Description	Triple single-pole double-throw analog switch

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Manufacturer	NXP [NXP Semiconductors]

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HEF4053B

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Product data sheet

Rev. 10 — 17 November 2011

11 of 20

NXP Semiconductors

HEF4053B

Triple single-pole double-throw analog switch

11.2 Additional dynamic parameters

[1]

fi is biased at 0.5 VDD; VI =0.5VDD (p-p).

11.2.1 Test circuits

Table 11.

Additional dynamic characteristics

VSS = VEE = 0 V; Tamb = 25 C.

Symbol

Parameter

Conditions

VDD

Typ

Max

Unit

THD

total harmonic distortion

see Figure 16; RL =10k; CL =15pF;

channel ON; VI =0.5VDD (p-p);

fi =1 kHz

5 V

[1] 0.25

-

%

10 V

[1] 0.04

-

%

15 V

[1] 0.04

-

%

f(3dB)

3 dB frequency response see Figure 17; R

L = 1 k; CL = 5 pF;

channel ON; VI =0.5VDD (p-p)

5 V

[1] 13

-

MHz

10 V

[1] 40

-

MHz

15 V

[1] 70

-

MHz



iso

isolation (OFF-state)

see Figure 18; fi = 1 MHz; RL = 1 k;

CL = 5 pF; channel OFF;

VI =0.5VDD (p-p)

10 V

[1]

50

-

dB

Vct

crosstalk voltage

digital inputs to switch; see Figure 19;

RL = 10 k; CL =15 pF;

E or Sn = VDD (square-wave)

10 V

50

-

mV

Xtalk

crosstalk

between switches; see Figure 20;

fi = 1 MHz; RL =1 k;

VI =0.5VDD (p-p)

10 V

[1]

50

-

dB

Table 12.

Dynamic power dissipation PD

PD can be calculated from the formulas shown; VEE = VSS =0 V; tr = tf  20 ns; Tamb = 25 C.

Symbol

Parameter

VDD

Typical formula for PD (W)

where:

PD

dynamic power

dissipation

5V

PD = 2500  fi + (fo  CL)  VDD2

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VDD = supply voltage in V;

(C

L  fo) = sum of the outputs.

10 V

PD = 11500  fi + (fo  CL)  VDD2

15 V

PD = 29000  fi + (fo  CL)  VDD2

Fig 16. Test circuit for measuring total harmonic

distortion

Fig 17. Test circuit for measuring frequency response

D

001aaj904

VSS

fi

RL

CL

switch

VSS = VEE

S1 to S3

E

nZ

nY0

VDD or VSS

VDD

nY1

1

2

dB

001aaj905

VSS

fi

RL

CL

switch

VSS = VEE

S1 to S3

E

nZ

nY0

VDD or VSS

VDD

nY1

1

2

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