©2002 Fairchild Semiconductor Corporation

Rev. B, January 2002

PSPICE Electrical Model

.SUBCKT ISL9N310AD3ST 2 1 3 ;

rev May 2001

CA 12 8 1.1e-9

CB 15 14 1.65e-9

CIN 6 8 1.7e-9

DBODY 7 5 DBODYMOD

DBREAK 5 11 DBREAKMOD

DPLCAP 10 5 DPLCAPMOD

EBREAK 11 7 17 18 31.3

EDS 14 8 5 8 1

EGS 13 8 6 8 1

ESG 6 10 6 8 1

EVTHRES 6 21 19 8 1

EVTEMP 20 6 18 22 1

IT 8 17 1

LDRAIN 2 5 1.00e-9

LGATE 1 9 4.88e-9

LSOURCE 3 7 1.85e-9

MMED 16 6 8 8 MMEDMOD

MSTRO 16 6 8 8 MSTROMOD

MWEAK 16 21 8 8 MWEAKMOD

RBREAK 17 18 RBREAKMOD 1

RDRAIN 50 16 RDRAINMOD 1.5e-3

RGATE 9 20 3.24

RLDRAIN 2 5 10

RLGATE 1 9 48.8

RLSOURCE 3 7 18.5

RSLC1 5 51 RSLCMOD 1e-6

RSLC2 5 50 1e3

RSOURCE 8 7 RSOURCEMOD 6e-3

RVTHRES 22 8 RVTHRESMOD 1

RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD

S1B 13 12 13 8 S1BMOD

S2A 6 15 14 13 S2AMOD

S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*550),3))}

.MODEL DBODYMOD D (IS = 1.5e-10 RS = 13.5e-3 ikf = 15 xti = .1 N = 1.1 TRS1 = 1.0e-3 TRS2 = 8.0e-7 CJO = 5.5e-10 TT =

2e-10 M = 0.35)

.MODEL DBREAKMOD D (RS = 0.068 TRS1 = 1.12e-3 TRS2 = 1.25e-6)

.MODEL DPLCAPMOD D (CJO = 4e-10 IS = 1e-30 N = 10 M = 0.31)

.MODEL MMEDMOD NMOS (VTO = 1.45KP = 7.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.24)

.MODEL MSTROMOD NMOS (VTO = 1.78KP = 100 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)

.MODEL MWEAKMOD NMOS (VTO = 1.13KP = 0.09 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 32.40 RS = 0.1)

.MODEL RBREAKMOD RES (TC1 = 1.01e-3 TC2 = 1.00e-7)

.MODEL RDRAINMOD RES (TC1 = 2.01e-2 TC2 = 4.0e-5)

.MODEL RSLCMOD RES (TC1 = 1.02e-4 TC2 = -1.13e-6)

.MODEL RSOURCEMOD RES (TC1 = 1.0e-3 TC2 = 1e-6)

.MODEL RVTHRESMOD RES (TC1 = 5.0e-4 TC2 = -7e-6)

.MODEL RVTEMPMOD RES (TC1 = -4.0e-3 TC2 = 1.25e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.5 VOFF= -1.5)

.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -1.5 VOFF= -2.5)

.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF= 0)

.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0 VOFF= -0.5)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global

Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank

Wheatley.

18

22

+

-

6

8

+

-

5

51

19

8

+

-

17

18

6

8

+

-

5

8

+

-

RBREAK

RVTEMP

VBAT

RVTHRES

IT

17

18

19

22

12

13

15

S1A

S1B

S2A

S2B

CA

CB

EGS

EDS

14

8

13

8

14

13

MWEAK

EBREAK

DBODY

RSOURCE

SOURCE

11

7

3

LSOURCE

RLSOURCE

CIN

RDRAIN

EVTHRES

16

21

8

MMED

MSTRO

DRAIN

2

LDRAIN

RLDRAIN

DBREAK

DPLCAP

ESLC

RSLC1

10

5

51

50

RSLC2

1

GATE

RGATE

EVTEMP

9

ESG

LGATE

RLGATE

20

+

-

+

-

+

-

6