LPC812M101JDH16 datasheet(9/71 Pages) NXP

Part #	LPC812M101JDH16

Description	32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash and 4 kB SRAM

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Manufacturer	NXP [NXP Semiconductors]

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LPC81xM

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Product data sheet

Rev. 3 — 29 July 2013

9 of 71

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

SWCLK/PIO0_3/

TCK

65

3

[2] I/O

I; PU

SWCLK — Serial Wire Clock. SWCLK is enabled by default on

this pin.

In boundary scan mode: TCK (Test Clock).

I/O

-

PIO0_3 — General purpose digital input/output pin.

PIO0_4/WAKEUP/

TRST

54

2

[6] I/O

I; PU

PIO0_4 — General purpose digital input/output pin.

In ISP mode, this is the USART0 transmit pin U0_TXD.

In boundary scan mode: TRST (Test Reset).

This pin triggers a wake-up from Deep power-down mode. If you

need to wake up from Deep power-down mode via an external

pin, do not assign any movable function to this pin. Pull this pin

HIGH externally to enter Deep power-down mode. Pull this pin

LOW to exit Deep power-down mode. A LOW-going pulse as

short as 50 ns wakes up the part.

RESET/PIO0_5

4

3

1

[4] I/O

I; PU

RESET — External reset input: A LOW-going pulse as short as

50 ns on this pin resets the device, causing I/O ports and

peripherals to take on their default states, and processor

execution to begin at address 0.

I-

PIO0_5 — General purpose digital input/output pin.

PIO0_6/VDDCMP

18

15

-

[9] I/O

I; PU

PIO0_6 — General purpose digital input/output pin.

AI

-

VDDCMP — Alternate reference voltage for the analog

comparator.

PIO0_7

17

14

-

[2] I/O

I; PU

PIO0_7 — General purpose digital input/output pin.

PIO0_8/XTALIN

14

11

-

[8] I/O

I; PU

PIO0_8 — General purpose digital input/output pin.

I-

XTALIN — Input to the oscillator circuit and internal clock

generator circuits. Input voltage must not exceed 1.95 V.

PIO0_9/XTALOUT

13

10

-

[8] I/O

I; PU

PIO0_9 — General purpose digital input/output pin.

O-

XTALOUT — Output from the oscillator circuit.

PIO0_10

9

8

-

[3] IIA

PIO0_10 — General purpose digital input/output pin. Assign I2C

functions to this pin when true open-drain pins are needed for a

signal compliant with the full I2C specification.

PIO0_11

8

7

-

[3] IIA

PIO0_11 — General purpose digital input/output pin. Assign I2C

functions to this pin when true open-drain pins are needed for a

signal compliant with the full I2C specification.

PIO0_12

3

2

-

[2] I/O

I; PU

PIO0_12 — General purpose digital input/output pin. ISP entry

pin on the SO20/TSSOP20/TSSOP16 packages starting with

chip version 4C (see Table 6). A LOW level on this pin during

reset starts the ISP command handler.

See pin PIO0_1 for the DIP8 package and chip versions 1A and

2A.

PIO0_13

2

1

-

[2] I/O

I; PU

PIO0_13 — General purpose digital input/output pin.

PIO0_14

20

-

[7] I/O

I; PU

PIO0_14 — General purpose digital input/output pin.

PIO0_15

11

-

[7] I/O

I; PU

PIO0_15 — General purpose digital input/output pin.

PIO0_16

10

-

[7] I/O

I; PU

PIO0_16 — General purpose digital input/output pin.

Table 4.

Pin description table (fixed pins)

Symbol

Type Reset

state

[1]

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