LIMITS

PARAMETER

SYMBOL

UNITS

MIN

TYP

MAX

CONTROL WORD TIMING

RECEIVER TIMING

FIFO TIMING

TRANSMISSION TIMING

LINE DRIVER OUTPUT TIMING

Pulse Width -

t

80

ns

Setup - DATA BUS Valid to

HIGH

t

50

ns

Hold -

HIGH to DATA BUS Hi-Z

t

10

ns

Delay - Start ARINC 32nd Bit to

LOW: High Speed

t

16

µs

Low Speed

t

128

µs

Delay -

LOW to

LOW

t

0

ns

Delay -

LOW to

HIGH

t

200

ns

Setup - SEL to

LOW

t

10

ns

Hold - SEL to

HIGH

t

10

ns

Delay -

LOW to DATA BUS Valid

t

50

100

ns

Delay -

HIGH to DATA BUS Hi-Z

t

30

ns

Pulse Width -

or

t

80

ns

Spacing -

HIGH to next

LOW

t

50

ns

Pulse Width -

or

t

80

ns

Setup - DATA BUS Valid to

HIGH

t

50

ns

Hold -

HIGH to DATA BUS Hi-Z

t

10

ns

Spacing -

or

t

0

ns

Delay -

HIGH to TX/R LOW

t

840

ns

Spacing -

HIGH to ENTX HIGH

t

0

µs

Delay - 32nd ARINC Bit to TX/R HIGH

t

50

ns

Spacing - TX/R HIGH to ENTX LOW

t

0

ns

Line driver transition differential times:

high to low

t

1.0

1.5

2.0

CWSTR

CWSTR

CWSTR

D/R

D/R

EN

EN

D/R

EN

EN

EN

EN

EN1

EN2

EN

EN

PL1

PL2

PL

PL

PL1

PL2

PL2

PL2

CWSTR

CWSET

CWHLD

D/R

D/R

D/REN

END/R

SELEN

ENSEL

ENDATA

DATAEN

EN

ENEN

PL

DWSET

DWHLD

PL12

TX/R

PL2EN

DTX/R

ENTX/R

fx

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed

t

25

µs

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed

t

200

µs

(High Speed)

µs

low to high

t

1.0

1.5

2.0

µs

(Low Speed)

high to low

t

5.0

10

15

µs

low to high

t

5.0

10

15

µs

Delay -

LOW to

LOW

t

0

ns

Hold -

HIGH to

HIGH

t

0

ns

Delay - TX/R LOW to ENTX HIGH

t

0

ns

t

400

ns

±1%

ENDAT

ENDAT

rx

fx

rx

ENPL

PLEN

TX/REN

MR

REPEATER OPERATION TIMING

MASTER RESET PULSE WIDTH

ARINC DATA RATE AND BIT TIMING

EN

PL

PL

EN

AC ELECTRICAL CHARACTERISTICS

Vcc = 5V, V+=10V, V- = -10V, GND = 0V, TA = Oper. Temp. Range and fclk = 1MHz 0.1% with 60/40 duty cycle

+

HI-8581, HI-8589

HOLT INTEGRATED CIRCUITS

11