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HI-3597PST-40 Datasheet(PDF) 6 Page - Holt Integrated Circuits |
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HI-3597PST-40 Datasheet(HTML) 6 Page - Holt Integrated Circuits |
6 / 18 page HI-3596, HI-3597, HI-3598, HI-3599 HOLT INTEGRATED CIRCUITS 6 ARINC 429 Data Format Control Register bit CR9 controls how individual bits in the received ARINC word are mapped to the HI-359x SPI data word during data read operations. Table 5 describes this mapping. Table 5. SPI / ARINC bit-mapping SPI / ARINC bit-mapping SPI Order 1 2 - 22 23 24 25 26 27 28 29 30 31 32 ARINC bit 32 31 - 11 10 9 1 2 3 4 5 6 7 8 CR9 = 0 Data ARINC bit 32 31 - 11 10 9 8 7 6 5 4 3 2 1 CR9 = 1 Data ARINC 429 Receiver ARINC Bus Interface Figure 3 shows the input circuit for each on-chip ARINC 429linereceiver.TheARINC429specificationrequires detection levels summarized in Table 6. Table 6. ARINC 429 Detection Levels STATE DIFFERENTIAL VOLTAGE ONE +6.5 Volts to +13 Volts NULL +2.5 Volts to -2.5 Volts ZERO -6.5 Volts to -13 Volts DIFFERENTIAL AMPLIFIERS COMPARATORS RINA-40 RINA RINB RINB-40 VDD GND VDD GND ONE NULL ZERO Figure 3. ARINC Receiver Input The HI-359x family guarantees recognition of these lev- els with a common mode Voltage with respect to GND less than ±30V for the worst case condition (3.15V sup- ply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. Receiver Logic Operation Figure4isablockdiagramshowingthelogicforeach receiver. Bit Timing TheARINC429specificationdefinestimingtolerances for received data according to Table 7. Table 7. ARINC 429 Receiver Timing Tolerances HIGH SPEED LOW SPEED Bit Rate 100Kbps ± 1% 12K - 14.5Kbps Pulse Rise Time 1.5±0.5μs 10±5μs Pulse Fall Time 1.5±0.5μs 10±5μs Pulse Width 5μs±5% 34.5to41.7μs |
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