FUNCTIONAL DESCRIPTION (cont.)

DATA RATE - EXAMPLE PATTERN

429DO

429DO

ARINC BIT

NULL

DATA

DATA

DATA

NULL

NULL

WORD GAP

BIT 1

NEXT WORD

BIT 32

BIT 31

BIT 30

LOADING CONTROL WORD

CWHLD

t

CWSET

t

CWSTR

t

DATA BUS

CWSTR

VALID

RECEIVER OPERATON

DATA READY FLAG

D/R

ARINC DATA

BYTE SELECT

SEL

ENABLE BYTE ON BUS

EN

DATA BUS

BIT 31

BIT 32

SELEN

t

D/R

t

ENSEL

t

DATAEN

t

D/REN

t

END/R

t

EN

t

ENSEL

t

SELEN

t

DATAEN

t

ENDATA

t

ENDATA

t

ENEN

t

DON'T CARE

DON'T CARE

DON'T CARE

BYTE 1 VALID

BYTE 2 VALID

TIMING DIAGRAMS

HI-8282A

REPEATER OPERATION

Repeater mode of operation allows a data word received by the

HI-8282 to be placed directly into the Transmit FIFO for

transmission.

After a 32-bit word has been shifted into the

receiver shift register, the

flag goes low. A logic "0" is placed

on the SEL line and

is strobed. This is the same procedure as

for normal receiver operation, placing the lower byte (16) of the

data word on the data bus. By strobing

at the same time as

D/R

EN

PL1

EN, the byte is also transferred into the Transmit FIFO.

SEL is

then taken high and

is strobed again to place the upper data

word byte onto the data bus. By strobing

at the same time as

, the second data word byte is also transferred to the Transmit

FIFO. The data word is now ready for transmission, according to

the parity programmed into the Control Word register.

In normal (non-repeater) operation, either byte of the received

data word may be read first by using the SEL input.

During

repeater operation however, data word lower byte must always be

read first. While the data is being read, it is loading concurrently

into the Transmit FIFO, which always loads lower byte first.

EN

PL2

EN

HOLT INTEGRATED CIRCUITS

6