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HI-3599PSTF-40 Datasheet(PDF) 9 Page - Holt Integrated Circuits |
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HI-3599PSTF-40 Datasheet(HTML) 9 Page - Holt Integrated Circuits |
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9 / 18 page  HI-3596, HI-3597, HI-3598, HI-3599 HOLT INTEGRATED CIRCUITS 9 comparedtothefirst(MSB)bitofeachSPI8-bitdata fieldfromSPIinstructionn1hex,where“n”isthechan- nel number 1-8 hex. IfachannelControlRegisterCR2bitequals”0,”thecor- responding receiver recognizes all label values as valid, as shown in Table 9. Reading the Label Memory Thecontentsofeachchannel’sLabelMemorymaybe read via the SPI interface using instruction n2 hex where “n”equalsthechannelnumber1-8hex,asdescribedin Table 2. Digital Transmit Function The Transmit Register can be used as a digital transmit- ter by connecting the TX1 and TX0 pins to an external ARINC 429 line driver such as the HI-8570 or HI-8571 (except HI-3599). Loopback Self-Test The HI-359x devices may use the Transmit Register toexecuteuser-definedself-testsequences(loopback test) for each receiver. This feature may be individually enabled for each receiver by resetting Control Register CR5bitto“0”.A32-bittestwordisloadedtotheTrans- mit Register using SPI instructions n8 hex (for ARINC 429 high-speed data rate) or n9 hex (for ARINC 429 low speed). Upon completion of the instruction, the word is shifted out of the register and routed to all receivers. If self-test mode is enabled and the receive channel is set to the correct speed, each channel will receive the test word as if it came from an external ARINC 429 bus.Ifloopbackisnotenabled,thechannelignoresthe self-test word and continues to respond to the external ARINC 429 bus ( Note: In the case of HI-3597, RIN1A and RIN1B pins are not available). In all cases, the serial test word may be observed at the TX1 and TX0 pins (except HI-3599), as shown in Table 10. NOTE:ThefirstbitshiftedintotheSelfTestregisterwill bethefirstbitsenttothereceiversandtheTX1andTX0 pins. In ARINC 429 protocol, this bit is the LSB. Table 10. Test Outputs TX1 TX0 ARINC 429 State 0 0 NULL 1 0 ONE 0 1 ZERO Line Receiver Input Pins The HI-3598 has two sets of Line Receiver input pins, RINA/B and RINA/B-40. Only one pair may be used to connect to the ARINC 429 bus. THE RINA/B pins may be connected directly to the ARINC 429 bus. The RINA/B-40pinsrequireanexternal40KΩresistortobe added in series with each ARINC input without affect- ing the ARINC input thresholds. This option is especially useful in applications where lightning protection circuitry is also required. When using the RINA/B-40 pins, each side of the ARINC busmustbeconnectedthrougha40KΩseriesresistor in order for the chip to detect the correct ARINC levels. The typical 10V differential signal is translated and input to a window comparator and latch. The comparator lev- elsaresetsothatwiththeexternal40KΩresistors,they are just below the standard 6.5V minimum ARINC data threshold and just above the standard 2.5V maximum ARINC null threshold. When using HI-3596, HI-3597 or HI-3599, only one set of ARINC 429 receive inputs are provided for each chan- nel. The standard HI-3596, HI-3597 and HI-3599 use the direct-connection RINA / RINB pins. The HI-3596-40, HI-3597-40 and HI-3599-40 devices use the RINA-40 / RINB-40 pins and require external 40KΩ series resis- tors. See the Ordering Information table for complete part number options. Please refer to the Holt AN-300 Application Note for additional information and recommendations on light- ning protection of Holt line drivers and line receivers. Master Reset (MR) Assertion of Master Reset (MR) causes immediate ter- mination of data reception. The eight Receive FIFOs arecleared.StatusRegisterFIFOflagsandFIFOstatus output signals are also cleared. Master Reset does not affect the eight channel Control Registers. Master Reset may be asserted using the MR input pin (HI-3596 and HI-3598 only) or by executing SPI instruction n7 hex. An individual receive channel can be reset by setting itscorrespondingControlRegisterCR3bitto“1”.This clears the channel’s receiver logic and Receive FIFO anddisablesthereceiveruntilCR3isresetto“0”.For applications requiring less than eight channels, unused receivers should be held in reset by setting the corre- sponding Control Register CR3 bits. |
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