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HI-3596PSTF-40 Datasheet(PDF) 7 Page - Holt Integrated Circuits |
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HI-3596PSTF-40 Datasheet(HTML) 7 Page - Holt Integrated Circuits |
7 / 18 page HI-3596, HI-3597, HI-3598, HI-3599 HOLT INTEGRATED CIRCUITS 7 The HI-359x family accept signals within these toler- ances and rejects signals outside these tolerances. Receiver logic achieves this as described below: 1. Anaccurate1MHzclocksourceisrequiredtovali- date the receive signal timing. Less than 0.1% error is recommended. 2. The receiver uses three separate 10-bit sampling shift registers for Ones detection, Zeros detection and Null detection. When the input signal is within thedifferentialvoltagerangeforanyshiftregister’s state(OneZeroorNull)samplingclocksahighbit into that register. When the receive signal is outside the differential voltage range defined for any shift register,alowbitisclocked.Onlyoneshiftregister canclockahighbitforanygivensample.Allthree registersclocklowbitsifthedifferentialinputvolt- ageisbetweendefinedstatevoltagebands. Valid data bits require at least three consecutive One or Zero samples (three high bits) in the upper half of the Ones or Zeros sampling shift register, and at least three consecutive Null samples (three high bits) in the lower half of the Null sampling shift regis- ter within the data bit interval. A word gap Null requires at least three consecutive Null samples (three high bits) in the upper half of the Null sampling shift register and at least three con- secutive Null samples (three high bits) in the lower half of the Null sampling shift register. This guaran- tees the minimum pulse width. FIFO LOAD CONTROL CONTROL BITS CR2, CR6-8 / SPI INTERFACE 32-BIT SHIFT REGISTER ACLK BIT COUNTER AND END OF SEQUENCE 32ND BIT DATA BIT CLOCK WORD GAP BIT CLOCK END START SEQUENCE CONTROL ERROR CLOCK NULL ZEROS SHIFT REGISTER ONES EOS LABEL / DECODE COMPARE 16-label Memory 4 words x 32-bit FIFO FLAG SCK CS SI SO PARITY CHECK SHIFT REGISTER SHIFT REGISTER ERROR DETECTION WORD GAP TIMER Figure 4. ReceiverBlockDiagram |
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