PIN DESCRIPTION

HI-8282A

SYMBOL

FUNCTION

DESCRIPTION

VCC

POWER

+5V ±5%

429DI1 (A)

INPUT

ARINC receiver 1 positive input

429DI1 (B)

INPUT

ARINC receiver 1 negative input

429DI2 (A)

INPUT

ARINC receiver 2 positive input

429DI2 (B)

INPUT

ARINC receiver 2 negative input

OUTPUT

Receiver 1 data ready flag

OUTPUT

Receiver 2 data ready flag

SEL

INPUT

Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)

INPUT

Data Bus control, enables receiver 1 data to outputs

INPUT

Data Bus control, enables receiver 2 data to outputs if

is high

BD15

I/O

Data Bus

BD14

I/O

Data Bus

BD13

I/O

Data Bus

BD12

I/O

Data Bus

BD11

I/O

Data Bus

BD10

I/O

Data Bus

BD09

I/O

Data Bus

BD08

I/O

Data Bus

BD07

I/O

Data Bus

BD06

I/O

Data Bus

GND

POWER

0 V

BD05

I/O

Data Bus

BD04

I/O

Data Bus

BD03

I/O

Data Bus

BD02

I/O

Data Bus

BD01

I/O

Data Bus

BD00

I/O

Data Bus

INPUT

Latch enable for byte 1 entered from data bus to transmitter FIFO.

INPUT

Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow

.

TX/R

OUTPUT

Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high

after transmission and FIFO empty.

429DO

OUTPUT

"ONES" data output from transmitter.

OUTPUT

"ZEROES" data output from transmitter.

ENTX

INPUT

Enable Transmission

INPUT

Clock for control word register

CLK

INPUT

Master Clock input

TX CLK

OUTPUT

Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.

INPUT

Master Reset, active low

D/R1

D/R2

EN1

EN2

EN1

PL1

PL2

PL1

429DO

CWSTR

MR

HOLT INTEGRATED CIRCUITS

2