AC ELECTRICAL CHARACTERISTICS

Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz 0.1% with 60/40 duty cycle

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LIMITS

PARAMETER

SYMBOL

UNITS

MIN

TYP

MAX

CONTROL WORD TIMING

RECEIVER TIMING

FIFO TIMING

TRANSMISSION TIMING

Pulse Width -

t

130

ns

Setup - DATA BUS Valid to

HIGH

t

130

ns

Hold -

HIGH to DATA BUS Hi-Z

t

0

ns

Delay - Start ARINC 32nd Bit to

LOW: High Speed

t

16

µs

Low Speed

t

128

µs

Delay -

LOW to

L0W

t

0

ns

Delay -

LOW to

HIGH

t

200

ns

Setup - SEL to

L0W

t

20

ns

Hold - SEL to

HIGH

t

20

ns

Delay -

L0W to DATA BUS Valid

t

200

ns

Delay -

HIGH to DATA BUS Hi-Z

t

30

ns

Pulse Width -

or

t

200

ns

Spacing -

HIGH to next

L0W

t

50

ns

Pulse Width -

or

t

200

ns

Setup - DATA BUS Valid to

HIGH

t

110

ns

Hold -

HIGH to DATA BUS Hi-Z

t

10

ns

Spacing -

or

t

0

ns

Delay -

HIGH to TX/R LOW

t

840

ns

Spacing -

HIGH to ENTX HIGH

t

0

µs

Delay - 32nd ARINC Bit to TX/R HIGH

t

400

ns

Spacing - TX/R HIGH to ENTX L0W

t

0

ns

CWSTR

CWSTR

CWSTR

D/R

D/R

EN

EN

D/R

EN

EN

EN

EN

EN1

EN2

EN

EN

PL1

PL2

PL

PL

PL1

PL2

PL2

PL2

CWSTR

CWSET

CWHLD

D/R

D/R

D/REN

END/R

SELEN

ENSEL

ENDATA

DATAEN

EN

ENEN

PL

DWSET

DWHLD

PL12

TX/R

PL2EN

DTX/R

ENTX/R

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): High Speed

t

25

µs

Delay - ENTX HIGH to TXA(OUT) or TXB(OUT): Low Speed

t

200

µs

Delay -

LOW to

LOW

t

0

ns

Hold -

HIGH to

HIGH

t

0

ns

Delay - TX/R LOW to ENTX HIGH

t

0

ns

t

200

ns

±1%

ENDAT

ENDAT

ENPL

PLEN

TX/REN

MR

REPEATER OPERATION TIMING

Master Reset Pulse Width

ARINC Data Rate and Bit Timing

EN

PL

PL

EN

HI-8282A

HOLT INTEGRATED CIRCUITS

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