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MC9S12DJ512 Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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MC9S12DJ512 Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 124 page Freescale reserves the right to make changes without further notice to any products herein to improve reliability, function or design.Freescale does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.Freescale products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale was negligent regarding the design or manufacture of the part. DOCUMENT NUMBER 9S12DP512DGV1/D Revision History Version Number Revision Date Effective Date Author Description of Changes V01.00 27 Nov 2001 11 Feb 2002 - Initial version based on DP256 V2.09. V01.01 13 Mar 2002 13 Mar 2002 - Updated document formats. - Removed reference to SIM in overview. - Changed XCLKS to PE7 in signal description. - Removed "Oscillator start-up time from POR or STOP" from Oscillator Characterisitcs. - Changed VDD and VDDPLL to 2.35V. - Updated CINS. - Updated IOL/IOH values. - Updated input capacitance. - Updated NVM timing characteristics. V01.02 02 Apr 2002 02 Apr 2002 - Updated document reference (SPI, SCI). V01.03 15 Apr 2002 15 Apr 2002 - Corrected values in device memory map (RAM start, flash protected sector sizes). - Updated document reference (SCI). V01.04 06 Jun 2002 06 Jun 2002 - Changed all operating frequency references to 50MHz EXTAL and removed references to 80 pin LQFP. V01.05 05 Jul 2002 05 Jul 2002 - Preface Table "Document References": Changed to full naming for each block. - Table "Interrupt Vector Locations", Column "Local Enable": Corrected several register and bit names. - Table "Signal Properties": Added column "Internal Pull Resistor". - Table "PLL Characteristics": Updated parameters K1 and f1 - Figure "Basic Pll functional diagram": Inserted XFC pin in diagram - Enhanced section "XFC Component Selection" - Added to Sections ATD, ECT and PWM: freeze mode = active BDM mode. |
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