 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
5M80ZT64I5N Datasheet(PDF) 10 Page - Altera Corporation |
|
||||||||||||||||||||||||||||||
5M80ZT64I5N Datasheet(HTML) 10 Page - Altera Corporation |
|
|
10 / 166 page  1–2 Chapter 1: MAX V Device Family Overview Feature Summary MAX V Device Handbook May 2011 Altera Corporation ■ I/Os are fully compliant with the PCI-SIG® PCI Local Bus Specification, revision 2.2 for 3.3-V operation ■ Hot-socket compliant ■ Built-in JTAG BST circuitry compliant with IEEE Std. 1149.1-1990 Table 1–1 lists the MAX V family features. MAX V devices accept 1.8 V on their VCCINT pins. The 1.8-V VCCINT external supply powers the device core directly. MAX V devices operate internally at 1.8 V. The supported MultiVolt I/O interface voltage levels (VCCIO) are 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V. MAX V devices are available in two speed grades: –4 and –5, with –4 being the fastest. For commercial applications, speed grades –C4 and –C5 are available. For industrial and automotive applications, speed grade –I5 and –A5 are available, respectively. These speed grades represent the overall relative performance, not any specific timing parameter. f For propagation delay timing numbers within each speed grade and density, refer to the DC and Switching Characteristics for MAX V Devices chapter. MAX V devices are available in space-saving FineLine BGA (FBGA), Micro FineLine BGA (MBGA), plastic enhanced quad flat pack (EQFP), and thin quad flat pack (TQFP) packages (refer to Table 1–2 and Table 1–3). MAX V devices support vertical migration within the same package (for example, you can migrate between the 5M570Z, 5M1270Z, and 5M2210Z devices in the 256-pin FineLine BGA package). Vertical migration means that you can migrate to devices whose dedicated pins and JTAG pins are the same and power pins are subsets or supersets for a given package across device densities. The largest density in any package has the highest number of power pins; you must lay out for the largest planned density in a package to provide Table 1–1. MAX V Family Features Feature 5M40Z 5M80Z 5M160Z 5M240Z 5M570Z 5M1270Z 5M2210Z LEs 40 80 160 240 570 1,270 2,210 Typical Equivalent Macrocells 32 64 128 192 440 980 1,700 User Flash Memory Size (bits) 8,192 8,192 8,192 8,192 8,192 8,192 8,192 Global Clocks 444 44 44 Internal Oscillator 1 1 1 1 1 1 1 Maximum User I/O pins 54 79 79 114 159 271 271 tPD1 (ns) (1) 7.5 7.5 7.5 7.5 9.0 6.2 7.0 fCNT (MHz) (2) 152 152 152 152 152 304 304 tSU (ns) 2.3 2.3 2.3 2.3 2.2 1.2 1.2 tCO (ns) 6.5 6.5 6.5 6.5 6.7 4.6 4.6 Notes to Table 1–1: (1) tPD1 represents a pin-to-pin delay for the worst case I/O placement with a full diagonal path across the device and combinational logic implemented in a single LUT and LAB that is adjacent to the output pin. (2) The maximum global clock frequency, fCNT, is limited by the I/O standard on the clock input pin. The 16-bit counter critical delay will run faster than this number. |
Similar Part No. - 5M80ZT64I5N |
|
Similar Description - 5M80ZT64I5N |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
