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HI-3585PQM Datasheet(PDF) 3 Page - Holt Integrated Circuits |
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HI-3585PQM Datasheet(HTML) 3 Page - Holt Integrated Circuits |
3 / 19 page Example: one SPI Instruction op code 07hex data field 02hex MSB LSB MSB LSB CS SCK SI INSTRUCTIONS Instruction op codes are used to read, write and configure the HI- 3585. When goes low, the next 8 clocks at the SCK pin shift an instruction op code into the decoder, starting with the first positive edge. The op code is fed into the SI pin most significant bit first. For write instructions, the most significant bit of the data word must immediately follow the instruction op code and is clocked into its register on the next rising SCK edge. Data word length varies depending on word type written: 16-bit writes to Control Register, 32-bit ARINC word writes to transmit FIFO or 256-bit writes to the label-matching enable/disable table. CS For read instructions, the most significant bit of the requested data word appears at the SO pin after the last op code bit is clocked into the decoder, at the next falling SCK edge. As with write instructions, data field bit-length varies with read instruction type. Table 1 lists all instructions. Instructions that perform a reset or set, or enable transmission are executed after the last SI bit is received while is still low. CS OP CODE Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 DATA FIELD None None None None 8 bits 8 bits 256 bits 8 bits 32 bits None 8 bits 16 bits 8 bits 256 bits N x 32 Bits None 16 bits None None DESCRIPTION No instruction implemented After the 8th op code bit is received, perform Master Reset (MR) , reset all label selections , set all the label selections Reset the label at the address specified in the data field Set Starting with label FF hex, consecutively set or reset each label in descending order For example, a Data Field pattern starting with 1011 will set labels FF, FD, and FC hex and reset label FE hex Programs a division of the ACLK input. If the divided ACLK frequency is 1 MHz and Control Register bit CR1 is set, the ARINC receiver and transmitter operate from the divided ACLK clock. Allowable values for division rate are X1, X2, X4, X8, or XA hex. Any other programmed value results in no clock. Note: ACLK input frequency and division ratio must yield 1 MHz clock. Read the next word in the Receive FIFO. If the FIFO is empty, it will read zeros No Instruction Implemented Read the Status Register Read the Control Register Read the ACLK divide value programmed previously using op code 07 hex Read the Label look-up memory table consecutively starting with address FF hex. Write up to 32 words into the next empty positions of the Transmit FIFO No instruction implemented Write the Control Register Reset the Transmit FIFO. , the transmit FIFO will be empty Transmission enabled by this instruction only if Control Register bit 13 is zero After the 8th op code bit is received After the 8th op code bit is received the label at the address specified in the data field After the 8th op code bit is received TABLE 1. DEFINED INSTRUCTION OP CODES HI-3585, HI-3586 HOLT INTEGRATED CIRCUITS 3 |
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