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HI-3282BPQTF-10 Datasheet(PDF) 3 Page - Holt Integrated Circuits |
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HI-3282BPQTF-10 Datasheet(HTML) 3 Page - Holt Integrated Circuits |
3 / 14 page ARINC 429 DATA FORMAT The following table shows the bit positions in exchanging data with the receiver or the transmitter. ARINC bit 1 is the first bit transmitted or received. DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC 13 12 11 10 9 31 30 32 12345678 BIT BYTE 1 FUNCTIONAL DESCRIPTION DATA BUS FUNCTION CONTROL DESCRIPTION PIN BD04 PAREN Enables parity bit insertion into Transmitter data bit 32 If enabled, an internal connection BDO5 SELF TEST 0 = ENABLE is made passing 429DO and to the receiver logic inputs RECEIVER 1 If enabled, ARINC bits 9 and, BDO6 DECODER 1 = ENABLE 10 must match the next two control word bits If Receiver 1 Decoder is BDO7 - - enabled, the ARINC bit 9 must match this bit If Receiver 1 Decoder is BDO8 - - enabled, the ARINC bit 10 must match this bit RECEIVER 2 If enabled, ARINC bits 9 and BDO9 DECODER 1 = ENABLE 10 must match the next two control word bits If Receiver 2 Decoder is BD10 - - enabled, then ARINC bit 9 must match this bit If Receiver 2 Decoder is BD11 - - enabled, then ARINC bit 10 must match this bit INVERT Logic 0 enables normal odd parity BD12 XMTR 1 = ENABLE and Logic 1 enables even parity PARITY output in transmitter 32nd bit BD13 XMTR DATA 0 = ÷10 CLK is divided either by 10 or CLK SELECT 1 = ÷80 80 to obtain XMTR data clock BD14 RCVR DTA 0 = ÷10 CLK is divided either by 10 or CLK SELECT 1 = ÷80 80 to obtain RCVR data clock 429DO CONTROL WORD REGISTER The HI-3282 contains 11 data flip flops whose D inputs are con- nected to the data bus and clocks connected to . Each flip flop provides options to the user as follows: CWSTR RECEIVERS ARINC BUS INTERFACE Figure 1 shows the input circuit for each receiver. The ARINC 429 specification requires the following detection levels: The HI-3282 guarantees recognition of these levels with a common mode Voltage with respect to GND less than ±5V for the worst case condition (4.75V supply and 13V signal level). The tolerances in the design guarantee detection of the above levels, so the actual acceptance ranges are slightly larger. If the ARINC signal is out of the actual acceptance ranges, including the nulls, the chip rejects the data. STATE DIFFERENTIAL VOLTAGE ONE +6.5 Volts to +13 Volts NULL +2.5 Volts to -2.5 Volts ZERO -6.5 Volts to -13 Volts RECEIVER LOGIC OPERATION Figure 2 shows a block diagram of the logic section of each receiver. BYTE 2 DATA BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BUS 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 ARINC 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 BIT HI-3282, HI-3282B vcc vcc GND GND 429DI1 (B) 429DI2 (B) OR 429DI1 (A) 429DI2 (A) OR DIFFERENTIAL AMPLIFIERS ONES COMPARATORS NULL ZEROES FIGURE 1. ARINC RECEIVER INPUT HOLT INTEGRATED CIRCUITS 3 |
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