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HI-8685PSIF-10 Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-8685PSIF-10 Datasheet(HTML) 4 Page - Holt Integrated Circuits |
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4 / 12 page  HI-8685, HI-8686 ERROR CHECKING READING RECEIVE BUFFER Once a word gap is detected, the data word in the input register is transferred to the receive buffer and checked for errors. When parity detection is enabled (PARITY ENB high), the received word is checked for odd parity. If there is a parity error, the 32nd bit of the received data word is set high. If parity checking is disabled (PARITY ENB low) the 32nd bit of the data word is always the 32nd ARINC bit re- ceived. The ERROR flag output is set high upon receipt of a word gap and the number of bits received since the previous word gap is less than or greater than 32. The ERROR flag is reset low when the next valid ARINC word is written into the receive buffer or when is pulsed low. When the data word is transferred to the receive buffer, the DATA RDY pin goes high. The data word can then be read in two 16-bit bytes by pulsing the input low as indicated in Figure 5. The first read cycle resets DATARDY low and increments an internal counter to the second 16-bit byte. The relationship between each bit of an ARINC word received and each bit of the two 16-bit data bus bytes is specified in Figure 2. When a new ARINC word is received it always overwrites the receive buffer. If the first byte of the previous word has not been read, then previous data is lost and the receive buffer will contain the new ARINC word. How- ever, if the DATARDY pin goes high between the reading of the first and second bytes, the first byte is no longer valid because the corresponding second byte has been overwritten by the new ARINC word. Also, the next read will be of the first byte of the new ARINC word since the internal byte counter is always reset to the first byte when new data is transferred to the receive buffer. RESET READ FUNCTIONAL DESCRIPTION (cont.) TRUTH TABLE 1. RINA (-10) RINB (-10) TESTA TESTB RXA RXB -1.50V to +1.50V -1.50V to +1.50V 0 0 0 0 -3.25V to -6.50V +3.25V to +6.50V 0 0 0 1 +3.25V to +6.50V -3.25V to -6.50V 0 0 1 0 X X 0 101 X X 1 010 X X 1 100 X = don't care Read Byte Data Bus Bits ARINC Bits 1st Byte 1 D0 - D15 ARINC 1 - ARINC 16 2nd Byte 2 D0 - D15 ARINC 17 - ARINC 32 FIGURE 2. ORDER OF RECEIVED DATA RESET TEST MODE A low on the input sets a flip-flop which initializes the internal logic. When goes high, the internal logic remains in the initialized state until the first word gap is detected preventing reception of a partial word. The built-in differential line receiver can be disabled allow- ing the data and clock detection circuitry to be driven di- rectly with digital signals. The logical OR function of the TESTA and TESTB is defined in Truth Table 1. The two in- puts can be used for testing the receiver logic and for input- ting ARINC 429 type data derived from another source / pro- tocol. See Figure 4 for typical test input timing. The device should always be initialized with imme- diately after entering the test mode to clear a partial word that may have been received since the last word gap. Oth- erwise, an ERROR condition may occur and the first 32 bits of data on the test inputs may not be properly received. Also, when entering the test mode, both TESTA and TESTB should be set high and held in that state for at least one word gap period (17 gap clocks) after goes high. When exiting the test mode, both test inputs should be held low and the device initialized with RESET RESET RESET RESET RESET. HOLT INTEGRATED CIRCUITS 4 |
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