RECEIVER PARITY

The 32nd bit of received ARINC words stored in the receive FIFO

is used as a Parity Flag indicating whether good Odd parity is

received from the incoming ARINC word.

The parity bit is reset to indicate correct parity was received

and the resulting word is written to the receive FIFO.

The receiver sets the 32nd bit to a “1”, indicating a parity error

and the resulting word is then written to the receive FIFO.

Therefore, the 32nd bit retrieved from the receiver FIFO will always

be “0” when valid (odd parity) ARINC 429 words are received.

Odd Parity Received

Even Parity Received

0

X

0

X

Load FIFO

1

No

0

X

Ignore data

1

Yes

0

X

Load FIFO

0

X

1

No

Ignore data

0

X

1

Yes

Load FIFO

1

Yes

1

No

Ignore data

1

No

1

Yes

Ignore data

1

No

1

No

Ignore data

1

Yes

1

Yes

Load FIFO

CR2(3) ARINC word CR6(9) ARINC word

FIFO

matches

bits 9,10

label

match

CR7,8 (10,11)

FUNCTIONAL DESCRIPTION (cont.)

RETRIEVING DATA

Once 32 valid bits are recognized, the receiver logic generates an

End of Sequence (EOS). Depending upon the state of control

register bits CR2-CR11, the received ARINC 32-bit word is then

checked for correct decoding and label matching before being

loaded into the 32 x 32 receive FIFO. ARINC words which do not

meet the necessary 9th and 10th ARINC bit or label matching are

ignored and are not loaded into the receive FIFO. The following

table describes this operation.

HI-3582, HI-3583

HOLT INTEGRATED CIRCUITS

5