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HI-3282CDM-10 Datasheet(PDF) 4 Page - Holt Integrated Circuits

Part # HI-3282CDM-10
Description  ARINC 429 Serial Transmitter and Dual Receiver
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Manufacturer  HOLTIC [Holt Integrated Circuits]
Direct Link  http://www.holtic.com
Logo HOLTIC - Holt Integrated Circuits

HI-3282CDM-10 Datasheet(HTML) 4 Page - Holt Integrated Circuits

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BIT TIMING
The ARINC 429 specification contains the following timing
specification for the received data:
100K BPS ± 1% 12K -14.5K BPS
(HI-3282BPJx-xx only - 6.5K BPS min.)
1.5 ± 0.5 µsec
10 ± 5 µsec
1.5 ± 0.5 µsec
10 ± 5 µsec
5 µsec ± 5%
34.5 to 41.7 µsec
HIGH SPEED
LOW SPEED
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSE WIDTH
(HI-3282BPJx-xx only - 76.9 µsec max.)
The 32nd bit of received ARINC words stored in the receive FIFO
is used as a Parity Flag indicating whether good Odd parity is re-
ceived from the incoming ARINC word.
The parity bit is reset to indicate correct parity was received
and the resulting word is then written to the receive FIFO.
The receiver sets the 32nd bit to a “1”, indicating a parity error
and the resulting word is then written to the receive FIFO.
Therefore, the 32nd bit retrieved from the receiver FIFO will always
be a “0” when valid (odd parity) ARINC 429 words are received.
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then the EOS clocks the
RECEIVER PARITY
Odd Parity Received
Even Parity Received
RETRIEVING DATA
FUNCTIONAL DESCRIPTION (cont.)
SEL
EN
D/R
DECODER
CONTROL
BITS
/
MUX
CONTROL
LATCH
ENABLE
CONTROL
32 TO 16 DRIVER
32 BIT LATCH
32 BIT SHIFT REGISTER
TO PINS
CONTROL
BIT BD14
CLOCK
OPTION
CLOCK
CLK
BIT
COUNTER
AND
END OF
SEQUENCE
PARITY
CHECK
32ND
BIT
DATA
BIT CLOCK
EOS
WORD GAP
WORD GAP
TIMER
BIT CLOCK
END
START
SEQUENCE
CONTROL
ERROR
CLOCK
ERROR
DETECTION
SHIFT REGISTER
SHIFT REGISTER
NULL
ZEROS
SHIFT REGISTER
ONES
EOS
BITS9&10
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HI-3282, HI-3282B
data ready flag flip flop to a "1",
or
(or both) will go low.
The data flag for a receiver will remain low until after
ARINC
bytes from that receiver are retrieved. This is accomplished by
activating
with SEL, the byte selector, low to retrieve the first
byte and activating
with SEL high to retrieve the second byte.
retrieves data from receiver 1 and
retrieves data from
receiver 2. If another ARINC word is received and a new EOS
occurs before the two bytes are retrieved, the data is overwritten
by the new word.
D/R1
D/R2
EN
EN
EN1
EN2
both
INTERNAL LIGHTNING PROTECTION (-10 Only)
APPLICATION NOTE 300
The HI-3282-10 configurations are similar to the HI-3282 with the
exception that it allows an external 10K to 15K ohm resistor to be
added in series with each ARINC input without affecting the
ARINC input thresholds. This option is especially useful in
applications where lightning protection circuitry is also required.
The design of the HI-3282-10 device requires the external
10K to 15K ohm series resistors for proper ARINC level detection.
The typical 10 volt differential signal is translated and input to a
window comparator and latch. The comparator levels are set so
that, with the external 10K to 15K ohm resistors, they are just
below the standard 6.5 V minimum ARINC data threshold and just
above the 2.5 V maximum ARINC null threshold.
The receivers of the HI-3282-10 when used with external
15K ohm resistors will withstand DO-160F, Level 3, waveforms 3,
4, 5A and 5B.
No additional lightning protection circuit is
necessary.
Please refer to the Holt AN-300 Application Note for additional
information and recommendations on lightning protection of Holt
Line Drivers and Receivers.
HOLT INTEGRATED CIRCUITS
4


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