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5M80ZE64I4N Datasheet(PDF) 9 Page - Altera Corporation |
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5M80ZE64I4N Datasheet(HTML) 9 Page - Altera Corporation |
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9 / 166 page  MAX V Device Handbook May 2011 MV51001-1.2 Subscribe © 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. 1. MAX V Device Family Overview The MAX® V family of low cost and low power CPLDs offer more density and I/Os per footprint versus other CPLDs. Ranging in density from 40 to 2,210 logic elements (LEs) (32 to 1,700 equivalent macrocells) and up to 271 I/Os, MAX V devices provide programmable solutions for applications such as I/O expansion, bus and protocol bridging, power monitoring and control, FPGA configuration, and analog IC interface. MAX V devices feature on-chip flash storage, internal oscillator, and memory functionality. With up to 50% lower total power versus other CPLDs and requiring as few as one power supply, MAX V CPLDs can help you meet your low power design requirement. This chapter contains the following sections: ■ “Feature Summary” on page 1–1 ■ “Integrated Software Platform” on page 1–3 ■ “Device Pin-Outs” on page 1–3 ■ “Ordering Information” on page 1–4 Feature Summary The following list summarizes the MAX V device family features: ■ Low-cost, low-power, and non-volatile CPLD architecture ■ Instant-on (0.5 ms or less) configuration time ■ Standby current as low as 25 µA and fast power-down/reset operation ■ Fast propagation delay and clock-to-output times ■ Internal oscillator ■ Emulated RSDS output support with a data rate of up to 200 Mbps ■ Emulated LVDS output support with a data rate of up to 304 Mbps ■ Four global clocks with two clocks available per logic array block (LAB) ■ User flash memory block up to 8 Kbits for non-volatile storage with up to 1000 read/write cycles ■ Single 1.8-V external supply for device core ■ MultiVolt I/O interface supporting 3.3-V, 2.5-V, 1.8-V, 1.5-V, and 1.2-V logic levels ■ Bus-friendly architecture including programmable slew rate, drive strength, bus-hold, and programmable pull-up resistors ■ Schmitt triggers enabling noise tolerant inputs (programmable per pin) |
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