SIGNAL

FUNCTION

DESCRIPTION

VDD

POWER

+3.3V power supply pin

BD05

I/O

Data Bus

BD04

I/O

Data Bus

BD03

I/O

Data Bus

BD02

I/O

Data Bus

RIN1A

INPUT

ARINC receiver 1 positive input

RIN1B

INPUT

ARINC receiver 1 negative input

RIN2A

INPUT

ARINC receiver 2 positive input

RIN2B

INPUT

ARINC receiver 2 negative input

OUTPUT

Receiver 1 data ready flag

OUTPUT

FIFO full Receiver 1

OUTPUT

FIFO Half full, Receiver 1

OUTPUT

Receiver 2 data ready flag

OUTPUT

FIFO full Receiver 2

OUTPUT

FIFO Half full, Receiver 2

SEL

INPUT

Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)

INPUT

Data Bus control, enables receiver 1 data to outputs

INPUT

Data Bus control, enables receiver 2 data to outputs if

is high

BD15

I/O

Data Bus

BD14

I/O

Data Bus

BD13

I/O

Data Bus

BD12

I/O

Data Bus

BD11

I/O

Data Bus

BD10

I/O

Data Bus

BD09

I/O

Data Bus

BD08

I/O

Data Bus

BD07

I/O

Data Bus

BD06

I/O

Data Bus

GND

POWER

0 V

BD01

I/O

Data Bus

BD00

I/O

Data Bus

INPUT

Latch enable for byte 1 entered from data bus to transmitter FIFO.

INPUT

Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow

TX/R

OUTPUT

Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high

after transmission and FIFO empty.

OUTPUT

Transmitter FIFO Half Full

OUTPUT

Transmitter FIFO Full

V-

POWER

-9.5V to -10.5V

TXAOUT

OUTPUT

Line driver output - A side

TXBOUT

OUTPUT

Line driver output - B side

V+

POWER

+9.5V to +10.5V

ENTX

INPUT

Enable Transmission

INPUT

Clock for control word register

INPUT

Read Status Register if SEL=0, read Control Register if SEL=1

CLK

INPUT

Master Clock input

TX CLK

OUTPUT

Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.

INPUT

Master Reset, active low

TEST

INPUT

Disable Transmitter output if high (pull-down)

D/R1

FF1

HF1

D/R2

FF2

HF2

EN1

EN2

EN1

PL1

PL2

PL1.

HFT

FFT

CWSTR

RSR

MR

PIN DESCRIPTIONS

HI-3582A, HI-3583A

HOLT INTEGRATED CIRCUITS

2