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HI-3582 Datasheet(PDF) 3 Page - Holt Integrated Circuits |
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HI-3582 Datasheet(HTML) 3 Page - Holt Integrated Circuits |
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3 / 18 page  FUNCTIONAL DESCRIPTION CONTROL WORD REGISTER The HI-3582/HI-3583 contain a 16-bit control register which is used to configure the device. The control register bits CR0 - CR15 are loaded from BD00 - BD15 when is pulsed low. The control register contents are output on the databus when SEL = 1 and is pulsed low. Each bit of the control register has the following function: CWSTR RSR STATUS REGISTER The HI-3582/HI-3583 contain a 9-bit status register which can be interrogated to determine the status of the ARINC receivers, data FIFOs and transmitter. The contents of the status register are output on BD00 - BD08 when the pin is taken low and SEL = 0. Unused bits are output as Zeros. The following table defines the status register bits. RSR SR Bit FUNCTION STATE DESCRIPTION SR0 Data ready 0 Receiver 1 FIFO empty 1 Receiver 1 FIFO contains valid data Resets to zero when all data has been read. pin is the inverse of this bit (Receiver 1) SR1 FIFO half full 0 Receiver 1 FIFO holds less than 16 (Receiver 1) words 1 Receiver 1 FIFO holds at least 16 words. pin is the inverse of this bit. SR2 FIFO full 0 Receiver 1 FIFO not full (Receiver 1) 1 Receiver 1 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. pin is the inverse of this bit SR3 Data ready 0 Receiver 2 FIFO empty (Receiver 2) 1 Receiver 2 FIFO contains valid data Resets to zero when all data has been read. pin is the inverse of this bit SR4 FIFO half full 0 Receiver 2 FIFO holds less than 16 (Receiver 2) words 1 Receiver 2 FIFO holds at least 16 words. pin is the inverse of this bit. SR5 FIFO full 0 Receiver 2 FIFO not full (Receiver 2) 1 Receiver 2 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. pin is the inverse of this bit SR6 Transmitter FIFO 0 Transmitter FIFO not empty empty 1 Transmitter FIFO empty. SR7 Transmitter FIFO 0 Transmitter FIFO not full full 1 Transmitter FIFO full. pin is the inverse of this bit. SR8 Transmitter FIFO 0 Transmitter FIFO contains less than half full 16 words 1 Transmitter FIFO contains at least 16 words. pin is the inverse of this bit. D/R1 HF1 FF1 D/R2 HF2 FF2 FFT HFT CR Bit FUNCTION STATE DESCRIPTION CR0 Receiver 1 0 Data rate = CLK/10 Select 1 Data rate = CLK/80 Data clock CR1 Label Memory 0 Normal operation Read / Write 1 Load 16 labels using / Read 16 labels using / CR2 Enable Label 0 Disable label recognition Recognition (Receiver 1) 1 Enable label recognition CR3 Enable Label 0 Disable Label Recognition Recognition (Receiver 2) 1 Enable Label recognition CR4 Enable 0 Transmitter 32nd bit is data 32nd bit as parity 1 Transmitter 32nd bit is parity CR5 Self Test 0 The transmitter’s digital outputs are internally connected to the receiver logic inputs 1 Normal operation CR6 Receiver 1 0 Receiver 1 decoder disabled decoder 1 ARINC bits 9 and 10 must match CR7 and CR8 CR7 - - If receiver 1 decoder is enabled, the ARINC bit 9 must match this bit CR8 - - If receiver 1 decoder is enabled, the ARINC bit 10 must match this bit CR9 Receiver 2 0 Receiver 2 decoder disabled Decoder 1 ARINC bits 9 and 10 must match CR10 and CR11 CR10 - - If receiver 2 decoder is enabled, the ARINC bit 9 must match this bit CR11 - - If receiver 2 decoder is enabled, the ARINC bit 10 must match this bit CR12 Invert 0 Transmitter 32nd bit is Odd parity Transmitter parity 1 Transmitter 32nd bit is Even parity CR13 Transmitter 0 Data rate=CLK/10, O/P slope=1.5us data clock select 1 Data rate=CLK/80, O/P slope=10us CR14 Receiver 2 0 Data rate=CLK/10 data clock select 1 Data rate=CLK/80 CR15 Data 0 Scramble ARINC data format 1 Unscramble ARINC data PL1 PL2 EN1 EN2 HI-3582, HI-3583 HOLT INTEGRATED CIRCUITS 3 |
Similar Part No. - HI-3582_13 |
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Similar Description - HI-3582_13 |
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