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5AGXMA3G427C3ES Datasheet(PDF) 3 Page - Altera Corporation |
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5AGXMA3G427C3ES Datasheet(HTML) 3 Page - Altera Corporation |
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3 / 37 page  Description Feature • Native support for up to four signal processing precision levels: • Three 9 x 9, two 18 x 18, or one 27 x 27 multiplier in the same variable-precision DSP block • One 36 x 36 multiplier using two variable-precision DSP blocks (Arria V GZ devices only) • 64-bit accumulator and cascade for systolic finite impulse responses (FIRs) • Embedded internal coefficient memory • Preadder/subtractor for improved efficiency Variable-precision DSP Embedded Hard IP blocks DDR3 and DDR2 Memory controller (Arria V GX, GT, SX, and ST only) • Custom implementation: • Arria V GX and SX devices—up to 6.5536 Gbps • Arria V GT and ST devices—up to 10.3125 Gbps • Arria V GZ devices—up to 12.5 Gbps • PCI Express ® (PCIe®) Gen2 (x1, x2, or x4) and Gen1 (x1, x2, x4, or x8) hard IP with multifunction support, endpoint, and root port • PCIe Gen3 (x1, x2, x4, or x8) support (Arria V GZ only) • Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS) • Common Public Radio Interface (CPRI) PCS • Gigabit-capable passive optical network (GPON) PCS • 10-Gbps Ethernet (10GbE) PCS • Serial RapidIO ® (SRIO) PCS • Interlaken PCS Embedded transceiver I/O • Up to 650 MHz global clock network • Global, quadrant, and peripheral clock networks • Clock networks that are not used can be powered down to reduce dynamic power Clock networks • High-resolution fractional PLLs • Precision clock synthesis, clock delay compensation, and zero delay buffering (ZDB) • Integer mode and fractional mode • LC oscillator ATX transmitter PLLs (Arria V GZ only) Phase-locked loops (PLLs) Altera Corporation Arria V Device Overview Feedback 3 Summary of Arria V Features AV-51001 2013.05.06 |
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