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5AGXMA3D427I3ES Datasheet(PDF) 7 Page - Altera Corporation |
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5AGXMA3D427I3ES Datasheet(HTML) 7 Page - Altera Corporation |
7 / 37 page Package Plan Table 5: Package Plan for Arria V GX Devices—Preliminary F1517 (40 mm) F1152 (35 mm) F896 4 (31 mm) F672 (27 mm) Member Code XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO — — — — 9 416 9 336 A1 — — — — 9 416 9 336 A3 — — 24 544 18 384 9 336 A5 — — 24 544 18 384 9 336 A7 24 704 24 544 18 384 — — B1 24 704 24 544 18 384 — — B3 36 704 24 544 — — — — B5 36 704 24 544 — — — — B7 Arria V GT This section provides the available options, maximum resource counts, and package plan for the Arria V GT devices. Available Options Figure 2: Sample Ordering Code and Available Options for Arria V GT Devices—Preliminary Family Signature Embedded Hard IPs Transceiver Count Maximum channels Transceiver Speed Grade Package Type Package Code Operating Temperature FPGA Fabric Speed Grade Optional Suffix Indicates specific device options or shipment method GT : 10-Gbps transceivers M : 1 hard PCIe and 2 hard memory controllers F : Maximum 2 hard PCIe and 4 hard memory controllers 5A : Arria V C3 : 156K logic elements C7 : 242K logic elements D3 : 362K logic elements D7 : 504K logic elements D : 9 G : 18 H : 24 K : 36 3 : 10.3125 Gbps F : FineLine BGA (FBGA) 27 : 672 pins 31 : 896 pins 35 : 1,152 pins 40 : 1,517 pins 3 (fastest) 5 N : Lead-free packaging ES : Engineering sample 5A GT F D7 K 3 F 40 I 3 N Member Code Family Variant I : Industrial (TJ = -40° C to 100° C) 4 In the F896 package, the PCIe hard IP block on the right side of the Arria V GX A5, A7, B1, and B3 devices support x1 for Gen1 and Gen2 data rates. Altera Corporation Arria V Device Overview Feedback 7 Package Plan AV-51001 2013.05.06 |
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