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ERJ-3EKF3922V Datasheet(PDF) 4 Page - International Rectifier |
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ERJ-3EKF3922V Datasheet(HTML) 4 Page - International Rectifier |
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4 / 44 page  IR3827 4 www.irf.com © 2013 International Rectifier July 18, 2013 PIN DESCRIPTIONS PIN # PIN NAME PIN DESCRIPTION 1 Fb Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via a resistor divider to set the output voltage and to provide the feedback signal to the error amplifier. 2 N/C Should not be connected to other signals on PCB layout. It is internally connected for testing purpose. 3 Comp Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to Fb pin to form a loop compensator. 4, 17 Gnd Signal ground for internal reference and control circuitry. 5 Rt/Sync Multi-function pin to set the switching frequency. The internal oscillator frequency is set with a resistor between this pin and Gnd. Or synchronization to an external clock by connecting this pin to the external clock signal through a diode. 6 SS_Select Soft start selection pin. Three user selectable soft start time is available: 1.5ms (SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd) 7 PGood Open-drain power good indication pin. Connect a pull-up resistor from this pin to Vcc. 8 LDO_Select LDO output voltage selection pin. Float gives 5.1V and low 0V (Gnd) gives 6.9V 9 Vin Input for internal LDO. A 1.0µF capacitor should be connected between this pin and PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to Vcc/LDO_out pin. Connecting this pin to PVin can also implement the input voltage feedforward. 10 Vcc/LDO_Out Output of the internal LDO and optional input of an external biased supply voltage. A minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd. 11 PGnd Power Ground. This pin serves as a separated ground for the MOSFET drivers and should be connected to the system’s power ground plane. 12 SW Switch node. Connected this pin to the output inductor. 13 PVin Input voltage for power stage. 14 Boot Supply voltage for high side driver, a 100nF capacitor should be connected between this pin and SW pin. 15 Enable Enable pin to turn on and off the device. Input voltage monitoring (input UVLO) can also be implemented by connecting this pin to PVin pin through a resistor divider. 16 Seq Sequence pin to do simultaneous and ratiometric sequencing operation. A resistor divider can be connected from master output to this pin for sequencing mode of operation. If not used, leave it open. 17 Gnd Signal ground for internal reference and control circuitry. |
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