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GRM31CR61E226KE15L Datasheet(PDF) 4 Page - International Rectifier

Part # GRM31CR61E226KE15L
Description  16A Highly Integrated SupIRBuck Single-Input Voltage, Synchronous Buck Regulator
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Manufacturer  IRF [International Rectifier]
Direct Link  http://www.irf.com
Logo IRF - International Rectifier

GRM31CR61E226KE15L Datasheet(HTML) 4 Page - International Rectifier

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IR3448
4
www.irf.com
© 2013 International Rectifier
August 01, 2013
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
PVin
Input voltage for power stage. Bypass capacitors between PVin and
PGND should be connected very close to this pin and PGND; also forms
input to feedforward block
2
Boot
Supply voltage for high side driver
3
Enable
Enable pin to turning on and off the IC.
4
Rt/Sync
Use an external resistor from this pin to LGND to set the switching
frequency, very close to the pin. This pin can also be used for external
synchronization.
5
OCset
Current Limit setpoint. This pin allows the trip point to be set to one of
three possible settings by either floating this pin, tying it to VCC or tying it
to PGnd.
6
Vsns
Sense pin for OVP and PGood
7
FB
Inverting input to the error amplifier. This pin is connected directly to the
output of the regulator or to the output of the remote sense amplifier, via
resistor divider to set the output voltage and provide feedback to the
error amplifier.
8
COMP
Output of error amplifier. An external resistor and capacitor network is
typically connected from this pin to FB to provide loop compensation.
9
RSo
Remote Sense Amplifier Output
10, 26, 27,
29
PGND
Power ground. This pin should be connected to the system’s power
ground plane. Bypass capacitors between PVin and PGND should be
connected very close to PVIN pin (pin 1) and this pin.
11
LGND
Signal ground for internal reference and control circuitry.
12
RS-
Remote Sense Amplifier input. Connect to ground at the load.
13
RS+
Remote Sense Amplifier input. Connect to output at the load.
14
Cbyp
Bypassing capacitor for internal reference voltage. A capacitor between
100pF and 180pF should be connected between this pin and LGnd.
15, 19, 28,
30, 31, 33
NC
No connection.
16
PGD
Power Good status pin. Output is open drain. Connect a pull up resistor
from this pin to VCC.
17
Vin
Input Voltage for LDO.
18
VCC/LDO_out
Bias Voltage for IC and driver section, output of LDO. Add a minimum of
4.7uF bypass cap from this pin to PGnd.
20, 21, 22,
23, 24, 25,
32
SW
Switch node. This pin is connected to the output inductor.


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