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L6561D Datasheet(PDF) 4 Page - STMicroelectronics |
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L6561D Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 11 page OVER VOLTAGE PROTECTION OVP The output voltage is expected to be kept by the operation of the PFC circuit close to its nominal value. This is set by the ratio of the two external resistors R1 and R2 (see fig. 2), taking into con- sideration that the non inverting input of the error amplifier is biased inside the L6561 at 2.5V. In steady state conditions, the current through R1 and R2 is: IR1sc = Vout − 2.5 R1 = IR2 = 2.5V R2 and, if the external compensation network is made only with a capacitor Ccomp, the current through Ccomp equals zero. When the output voltage increases abruptly the current through R1 becomes: IR1 = Voutsc +∆VOUT − 2.5 R1 = IR1sc +∆IR1 Since the current through R2 does not change, ∆IR1 must flow through the capacitor Ccomp and enter the error amplifier. This current is monitored inside the L6561 and when reaches about 37 µA the output voltage of the multi- plier is forced to decrease, thus reducing the energy drawn from the mains. If the current exceeds 40 µA, the OVP protection is triggered (Dynamic OVP), and the external power transistor is switched off until the current falls approximately below 10 µA. However, if the overvoltage persists, an internal comparator (Static OVP) confirms the OVP condi- tion keeping the external power switch turned off (see fig. 1). Finally, the overvoltage that triggers the OVP function is: ∆Vout = R1 ⋅ 40µA. Typical values for R1,R2 and C are shown in the application circuits. The overvoltage can be set inde- pendently from the average output voltage. The pre- cision in setting the overvoltage threshold is 7% of ELECTRICAL CHARACTERISTICS (continued) ZERO CURRENT DETECTOR Symbol Pin Parameter Test Condition Min. Typ. Max. Unit VZCD 5 Input Threshold Voltage Rising Edge (1) 2.1 V Hysteresis (1) 0.3 0.5 0.7 V VZCD 5 Upper Clamp Voltage IZCD =20 µA 4.5 5.1 5.9 V VZCD 5 Upper Clamp Voltage IZCD = 3mA 4.7 5.2 6.1 V VZCD 5 Lower Clamp Voltage IZCD = –3mA 0.3 0.65 1 V IZCD 5 Sink Bias Current 1V ≤ VZCD ≤ 4.5V 2 µA IZCD 5 Source Current Capability -3 -10 mA IZCD 5 Sink Current Capability 3 10 mA VDIS 5 Disable threshold 150 200 250 mV IZCD 5 Restart Current After Disable VZCD < Vdis; VCC >VCCOFF -100 -200 -300 µA OUTPUT SECTION VGD 7 Dropout Voltage IGDsource = 200mA 1.2 2 V IGDsource = 20mA 0.7 1 V IGDsink = 200mA 1.5 V IGDsink = 20mA 0.3 V tr 7 Output Voltage Rise Time CL = 1nF 40 100 ns tf 7 Output Voltage Fall Time CL = 1nF 40 100 ns IGD off 7IGD Sink Current VCC =3.5V VGD = 1V 5 10 - mA OUTPUT OVERVOLTAGE SECTION IOVP 2 OVP Triggering Current 35 40 45 µA Static OVP Threshold 2.1 2.25 2.4 V RESTART TIMER tSTART Start Timer 70 150 400 µs (1) Parameter guaranteed by design, not tested in production. L6561 4/11 |
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