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R1QGA3618CB Datasheet(PDF) 11 Page - Renesas Technology Corp

Part # R1QGA3618CB
Description  36-Mbit DDRII SRAM 2-word Burst
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1QGA3618CB Datasheet(HTML) 11 Page - Renesas Technology Corp

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PAGE : 11
Rev. 0.09a : 2011.09.14
R1QBA36**CB* / R1QEA36**CB* Series
IIP
QVLD (Valid data indicator)
(R1QA, R1QB, R1QC, R1QD, R1QE, R1QF, R1QG, R1QH, R1QJ, R1QK, R1QL, R1QM
R1QN, R1QP series)
1. QVLD is provided on the QDR-II+ and DDR-II+ to simplify data capture on high speed systems. The Q
Valid indicates valid output data. QVLD is activated half cycle before the read data for the receiver to be
ready for capturing the data. QVLD is inactivated half cycle before the read finish for the receiver to stop
capturing the data. QVLD is edge aligned with CQ and /CQ.
6
-
3
(ODT disable)
0.6
RQ
Floating
2, 5
0.6
RQ
0.6
RQ
High
Thevenin equivalent resistance (R
THEV)
Unit
ODT range
(ODT disable)
Option 2
Notes:
1. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of
20 % is
175
RQ
350
.
2. Allowable range of RQ to guarantee impedance matching a tolerance of
20 % is
175
RQ
250
.
3. Allowable range of RQ for Option 1 to guarantee impedance matching a tolerance of
20 % is
175
RQ
250
.
4. At option 1, ODT control pin is connected to V
DDQ through 3.5 k
. Therefore it is recommended
to connect it to V
SS through less than 100
to make it low.
5. At option 2, ODT control pin is connected to V
SS through 3.5 k
. Therefore it is recommended to
connect it to
V
DDQ through less than 100
to make it high.
6. Renesas status: Option 1 = Available, Option 2 = Possible. If you need devices with option 2,
please contact Renesas sales office.
1, 4
0.3
RQ
Low
Notes
Option 1
ODT control pin
ODT (On Die Termination)
(R1QD, R1QE, R1QF, R1QK, R1QL, R1QM, R1QP series)
1. To reduce reflection which produces noise and lowers signal quality, the signals should be terminated,
especially at high frequency. Renesas offers ODT on the input signals to QDR-II+ and DDR-II+ family of
devices. (See the ODT pin table)
2. In ODT enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by
ODT control input. (See the ODT range table)
3. In DDR-II+ devices having common I/O bus, ODT is automatically enabled when the device inputs data
and disabled when the device outputs data.
4. There is no difference in AC timing characteristics between the SRAMs with ODT and SRAMs without
ODT.
5. There is no increase in the I
DD of SRAMs with ODT, however, there is an increase in the IDDQ (current
consumption from the I/O voltage supply) with ODT.
R10DS0159EJ0009


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