R1QGA7218AB datasheet(11/36 Pages) RENESAS

Part #	R1QGA7218AB

Description	72-Mbit QDR SRAM 2-word Burst

Download	36 Pages

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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11 / 36 page

Rev. 0.11 : 2013.01.15

R1Q2A7236ABB / R1Q2A7218ABB / R1Q2A7209ABB Series

PAGE:11

K Truth Table

Operation

K

/R

/W

D or Q

Write Cycle:

Load address, input write data

on consecutive K and /K rising

edges

×

L

Data in

Input

data

D(A+0)

D(A+1)

Input

clock

K(t)

/K(t)

Read Cycle:

Load address, output read data

on consecutive C and /C rising

edges

L

×

Data out

Output

data

Q(A+0)

Q(A+1)

Input

clock

for Q

RL*7=1.5

/C(t+1)

C(t+2)

RL=2.0

C(t+2)

/C(t+2)

RL=2.5

/C(t+2)

C(t+3)

NOP (No operation)

HH

D =

× or Q = High-Z

Standby (Clock stopped)

Stopped

×× Previous state

Notes:

1. H: high level, L: low level,

×: don’t care, : rising edge.

2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C and /C

rising edges, except if C and /C are high, then data outputs are delivered at K and /K rising

edges.

3. /R and /W must meet setup/hold times around the rising edges (low to high) of K and are

registered at the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up.

5. Refer to state diagram and timing diagrams for clarification.

6. When clocks are stopped, the following cases are recommended; the case of K = low, /K =

high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This

condition is not essential, but permits most rapid restart by overcoming transmission line

charging symmetrically.

7. RL = Read Latency (unit = cycle).

R10DS0164EJ0011

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