R1Q5A7236AB datasheet(10/36 Pages) RENESAS

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R1Q5A7236AB Datasheet(PDF) 10 Page - Renesas Technology Corp

Part #	R1Q5A7236AB

Description	72-Mbit QDR SRAM 2-word Burst

Download	36 Pages

Scroll/Zoom	100%

Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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10 / 36 page

Rev. 0.11 : 2013.01.15

R1Q2A7236ABB / R1Q2A7218ABB / R1Q2A7209ABB Series

PAGE:10

Common

DLL/PLL Constraints

1. DLL/PLL uses K clock as its synchronizing input. The input should have low phase jitter which is

specified as tKC var.

2. The lower end of the frequency at which the DLL/PLL can operate is 120 MHz.

(Please refer to AC Characteristics table for detail.)

3. When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.

Programmable Output Impedance

1. Output buffer impedance can be programmed by terminating the ZQ ball to V

SS through a precision resistor

(RQ). The value of RQ is five times the output impedance desired. The allowable range of RQ to

guarantee impedance matching with a tolerance of 15% is 250

Ω typical. The total external capacitance of

ZQ ball must be less than 7.5 pF.

R10DS0164EJ0011

Manufacturer	Part #	Datasheet	Description
Renesas Technology Corp	R1Q2A7236ABB	823Kb / 36P	72-Mbit QDR?줚I SRAM 2-word Burst
Renesas Technology Corp	R1Q2A7236ABG	825Kb / 36P	72-Mbit QDR?줚I SRAM 2-word Burst
Cypress Semiconductor	CY7C1510KV18	836Kb / 30P	72-Mbit QDR-II SRAM 2-Word Burst Architecture
	CY7C1510JV18	654Kb / 26P	72-Mbit QDR??II SRAM 2-Word Burst Architecture
	CY7C1512KV18	814Kb / 30P	72-Mbit QDR-II SRAM 2-Word Burst Architecture
	CY7C1510AV18	646Kb / 28P	72-Mbit QDR??II SRAM 2-Word Burst Architecture
	CY7C1510V18	494Kb / 27P	72-Mbit QDR-II??SRAM 2-Word Burst Architecture
	CY7C1510AV18	711Kb / 28P	72-Mbit QDR-II SRAM 2-Word Burst Architecture
Renesas Technology Corp	R1Q2A7236ABG	824Kb / 36P	72-Mbit QDR™II SRAM 2-word Burst 2013.01.15
Cypress Semiconductor	CY7C1510V18	369Kb / 24P	72-Mbit QDR-II??SRAM 2-Word Burst Architecture

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