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R1QBA3618CBB Datasheet(PDF) 7 Page - Renesas Technology Corp |
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R1QBA3618CBB Datasheet(HTML) 7 Page - Renesas Technology Corp |
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7 / 38 page  PAGE : 7 Rev. 0.10b : 2012.03.12 R1QBA36**C / R1QEA36**C Series 1 ODT control: When low; [Option 1] Low range mode is selected. The impedance range is between 52 and 105 (Thevenin equivalent), which follows 0.3 RQ for 175 RQ 350 . [Option 2] ODT is disabled. When high; High range mode is selected. The impedance range is between 105 and 150 (Thevenin equivalent), which follows 0.6 RQ for 175 RQ 250 . When floating; [Option 1] High range mode is selected. [Option 2] ODT is disabled. Input ODT (II+ only) Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. DQ and CQ output impedance are set to 0.2 RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to V DDQ, which enables the minimum impedance mode. This ball cannot be connected directly to V SS or left unconnected. In ODT (On Die Termination) enable devices, the ODT termination values tracks the value of RQ. The ODT range is selected by ODT control input. Input ZQ Valid output indicator: The Q Valid indicates valid output data. QVLD is edge aligned with CQ and /CQ. Output QVLD (II+ only) No connect: These pins can be left floating or connected to 0V V DDQ. NC Notes: 1. Renesas status: Option 1 = Available, Option 2 = Possible. 2. All power supply and ground balls must be connected for proper operation of the device. 2 2 2 Notes HSTL input reference voltage: Nominally V DDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffers. V REF Power supply: Ground. Supply V SS Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC Characteristics and Operating Conditions for range. Supply V DDQ Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions for range. Supply V DD IEEE 1149.1 test output: 1.8 V I/O level. Output TDO Synchronous echo clock outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when DQ tri- states. Output CQ, /CQ Synchronous data I/Os: Input data must meet setup and hold times around the rising edges of K and /K. Output data is synchronized to the respective C and /C, or to the respective K and /K if C and /C are tied high. The 9 device uses DQ0~DQ8. DQ9~DQ35 should be treated as NC pin. The 18 device uses DQ0~DQ17. DQ18~DQ35 should be treated as NC pin. The 36 device uses DQ0~DQ35. Input / output DQ 0 to DQ n Descriptions I/O type Name R10DS0193EJ0010 |
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