Rev. 0.11 : 2013.01.15

R1Q2A7236ABB / R1Q2A7218ABB / R1Q2A7209ABB Series

PAGE:9

72M_36M

Status

Power Up &

Unstable Stage

NOP &

Set-up Stage

Normal

Operation

V

DD

SET-UP Cycle

V

DDQ

V

REF

/DOFF

2. Double clock mode

K, /K

Fix High (=Vddq)

C, /C

Status

Power Up &

Unstable Stage

NOP &

Set-up Stage

Normal

Operation

V

DD

SET-UP Cycle

V

DDQ

V

REF

/DOFF

1. Single clock mode (C and /C pins fixed High)

K, /K

Fix High (=Vddq)

General Description

Power-up and Initialization Sequence

-V

- Recommended voltage application sequence : V

SS

V

DD

V

V

- Apply V

- Then execute either one of the following three sequences.

1. Single Clock Mode (C and /C tied high)

- Drive /DOFF high (/DOFF can be tied high from the start).

- Then provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+ series).

These meet the QDR common specification of 20 us.

When the operating frequency is less than 180 MHz, 2048 cycles are required (II series).

- Drive /DOFF high (/DOFF can be tied high from the start)

- Then provide stable clocks (K, /K , C, /C) for at least 1024 cycles (II series).

This meets the QDR common specification of 20 us.

When the operating frequency is less than 180 MHz, 2048 cycles are required (II series).

3. DLL/PLL Off Mode (/DOFF tied low)

- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 1024 cycles (II series) or 20 us (II+

series). These meet the QDR common specification of 20 us.

R10DS0164EJ0011