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FM25040B-GA Datasheet(PDF) 8 Page - Cypress Semiconductor |
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FM25040B-GA Datasheet(HTML) 8 Page - Cypress Semiconductor |
8 / 14 page FM25040B - Automotive Temp. Document Number: 001-86151 Rev. ** Page 8 of 14 Figure 9. Memory Write (WREN not shown) Figure 10. Memory Read Endurance The FM25040B devices are capable of being accessed at least 10 13 times, reads or writes. An F- RAM memory operates with a read and restore mechanism. Therefore, an endurance cycle is applied on a row basis for each access (read or write) to the memory array. The F-RAM architecture is based on an array of rows and columns. Rows are defined by A8-A3 and column addresses by A2-A0. See Block Diagram (pg 2) which shows the array as 64 rows of 64-bits each. The entire row is internally accessed once whether a single byte or all eight bytes are read or written. Each byte in the row is counted only once in an endurance calculation. The table below shows endurance calculations for 64-byte repeating loop, which includes an op-code, a starting address, and a sequential 64-byte data stream. This causes each byte to experience one endurance cycle through the loop. F-RAM read and write endurance is virtually unlimited even at 10MHz clock rate. Table 5. Time to Reach Endurance Limit for Repeating 64-byte Loop SCK Freq (MHz) Endurance Cycles/sec. Endurance Cycles/year Years to Reach Limit 10 18,660 5.88 x 10 11 17.0 5 9,330 2.94 x 10 11 34.0 1 1,870 5.88 x 10 10 170.1 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 op-code 0 0 0 0 A 0 1 1 MSB Byte Address 7 6 5 4 3 2 CS SCK SI SO 1 6 0 7 LSB MSB LSB Data Out 0 7 Hi-Z 7 6 5 4 3 2 1 0 LSB 0 1 2 3 4 5 6 7 0 1 2 3 4 5 0 1 2 3 4 5 6 7 op-code 0 0 0 0 A 0 1 0 MSB Byte Address 7 6 5 4 3 2 CS SCK SI SO 1 6 0 7 LSB MSB LSB Data 7 6 5 4 3 2 1 0 0 7 Hi-Z |
Similar Part No. - FM25040B-GA |
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Similar Description - FM25040B-GA |
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