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PD46365364BF1-E40Y-EQ1-A Datasheet(PDF) 8 Page - Renesas Technology Corp |
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PD46365364BF1-E40Y-EQ1-A Datasheet(HTML) 8 Page - Renesas Technology Corp |
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8 / 39 page  μPD46365084B, μPD46365094B, μPD46365184B, μPD46365364B R10DS0090EJ0400 Rev.4.00 Page 8 of 38 Nov 09, 2012 (2/2) Symbol Type Description CQ, CQ# Output Synchronous Echo Clock Outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and can be used as a data valid indication. These signals run freely and do not stop when Q tristates. If C and C# are stopped (if K and K# are stopped in the single clock mode), CQ and CQ# will also stop. ZQ Input Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. Q, CQ and CQ# output impedance are set to 0.2 x RQ, where RQ is a resistor from this bump to ground. The output impedance can be minimized by directly connect ZQ to VDDQ. This pin cannot be connected directly to GND or left unconnected. The output impedance is adjusted every 20 μs upon power-up to account for drifts in supply voltage and temperature. After replacement for a resistor, the new output impedance is reset by implementing power-on sequence. DLL# Input PLL Disable: When debugging the system or board, the operation can be performed at a clock frequency slower than TKHKH (MAX.) without the PLL circuit being used, if DLL# = LOW. The AC/DC characteristics cannot be guaranteed. For normal operation, DLL# must be HIGH and it can be connected to VDDQ through a 10 k Ω or less resistor. TMS TDI Input IEEE 1149.1 Test Inputs: 1.8 V I/O level. These balls may be left Not Connected if the JTAG function is not used in the circuit. TCK Input IEEE 1149.1 Clock Input: 1.8 V I/O level. This pin must be tied to VSS if the JTAG function is not used in the circuit. TDO Output IEEE 1149.1 Test Output: 1.8 V I/O level. When providing any external voltage to TDO signal, it is recommended to pull up to VDD. VREF − HSTL Input Reference Voltage: Nominally VDDQ /2. Provides a reference voltage for the input buffers. VDD Supply Power Supply: 1.8 V nominal. See Recommended DC Operating Conditions and DC Characteristics for range. VDDQ Supply Power Supply: Isolated Output Buffer Supply. Nominally 1.5 V. 1.8 V is also permissible. See Recommended DC Operating Conditions and DC Characteristics for range. VSS Supply Power Supply: Ground NC − No Connect: These signals are not connected internally. |
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