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PD46184182BF1-E40-EQ1 Datasheet(PDF) 4 Page - Renesas Technology Corp |
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PD46184182BF1-E40-EQ1 Datasheet(HTML) 4 Page - Renesas Technology Corp |
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4 / 34 page  μPD46184182B, μPD46184362B R10DS0114EJ0200 Rev.2.00 Page 4 of 34 Nov 09, 2012 Pin Arrangement 165-pin PLASTIC BGA (13 x 15) (Top View) [ μPD46184362B] 512K x 36 1 2 3 4 5 6 7 8 9 10 11 A CQ# VSS/144M NC/36M R, W# BW2# K# BW1# LD# A VSS/72M CQ B NC DQ27 DQ18 A BW3# K BW0# A NC NC DQ8 C NC NC DQ28 VSS A A0 A VSS NC DQ17 DQ7 D NC DQ29 DQ19 VSS VSS VSS VSS VSS NC NC DQ16 E NC NC DQ20 VDDQ VSS VSS VSS VDDQ NC DQ15 DQ6 F NC DQ30 DQ21 VDDQ VDD VSS VDD VDDQ NC NC DQ5 G NC DQ31 DQ22 VDDQ VDD VSS VDD VDDQ NC NC DQ14 H DLL# VREF VDDQ VDDQ VDD VSS VDD VDDQVDDQ VREF ZQ J NC NC DQ32 VDDQ VDD VSS VDD VDDQ NC DQ13 DQ4 K NC NC DQ23 VDDQ VDD VSS VDD VDDQ NC DQ12 DQ3 L NC DQ33 DQ24 VDDQ VSS VSS VSS VDDQ NC NC DQ2 M NC NC DQ34 VSS VSS VSS VSS VSS NC DQ11 DQ1 N NC DQ35 DQ25 VSS A A A VSS NC NC DQ10 P NC NC DQ26 A A C A A NC DQ9 DQ0 R TDO TCK A A A C# A A A TMS TDI A0, A : Address inputs TMS : IEEE 1149.1 Test input DQ0 to DQ35 : Data inputs / outputs TDI : IEEE 1149.1 Test input LD# : Synchronous load TCK : IEEE 1149.1 Clock input R, W# : Read Write input TDO : IEEE 1149.1 Test output BW0# to BW3# : Byte Write data select VREF : HSTL input reference input K, K# : Input clock VDD : Power Supply C, C# : Output clock VDDQ : Power Supply CQ, CQ# : Echo clock VSS : Ground ZQ : Output impedance matching NC : No connection DLL# : PLL disable NC/xxM : Expansion address for xxMb Remarks 1. ×××# indicates active LOW. 2. Refer to Package Dimensions for the index mark. 3. 2A, 3A and 10A are expansion addresses : 3A for 36Mb : 3A and 10A for 72Mb : 3A, 10A and 2A for 144Mb 2A and 10A of this product can also be used as NC. |
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