PD46184182BF1-E33-EQ1-A datasheet(11/34 Pages) RENESAS

Part #	PD46184182BF1-E33-EQ1-A

Description	18M-BIT DDR II SRAM 2-WORD BURST OPERATION

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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11 / 34 page

μPD46184182B, μPD46184362B

R10DS0114EJ0200 Rev.2.00

Page 11 of 34

Nov 09, 2012

Bus Cycle State Diagram

Remarks 1. A0 is internally advanced in accordance with the burst order table.

Bus cycle is terminated after burst count = 2.

2. State machine control timing sequence is controlled by K.

READ DOUBLE

Count = Count + 2

WRITE DOUBLE

Count = Count + 2

Power UP

Write

NOP

Supply voltage provided

LOAD NEW

ADDRESS

Count = 0

NOP

Load, Count = 2

Read

Load, Count = 2

Load

NOP,

Count = 2

NOP,

Count = 2

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