ISL97672A

9

FN7710.2

May 2, 2011

Theory of Operation

PWM Boost Converter

The current mode PWM boost converter produces the minimal

voltage needed to enable the LED stack with the highest forward

voltage drop to run at the programmed current. The ISL97672A

employs current mode control boost architecture that has a fast

current sense loop and a slow voltage feedback loop. Such

architecture achieves a fast transient response that is essential

for notebook backlight applications in which drained batteries

can be instantly changed to an AC/DC adapter without

noticeable visual disturbance. The number of LEDs that can be

driven by ISL97672A depends on the type of LED chosen in the

application. The ISL97672A is capable of boosting up to 45V and

typically driving 13 LEDs in series for each of the 8 channels,

enabling a total of 104 pieces of the 3.2V/20mA type of LEDs.

Enable

The Enable pin is used to enable the device. If there is no signal for

longer than 28ms, the device enters shutdown. The Enable pin

should not float. If it does, a 10k or higher pull-down resistor should

be added.

The Overvoltage Protection (OVP) pin has a function of setting the

range.

that:

35V.

then the OVP level must be reduced. Users should follow the

headroom control will be disturbed such that the channel voltage

can be much higher than expected. This can sometimes prevent

the driver from operating properly.

The ratio of the OVP capacitors should be the inverse of the OVP

Current Matching and Current Accuracy

Each channel of the LED current is regulated by the current

source circuit, as shown in Figure 21.

of the current source MOSFETs are designed to run at 500mV to

optimize power loss versus accuracy requirements. The sources

of errors of the channel-to-channel current matching come from

the op amp’s offset, internal layout, and reference, and these

parameters are optimized for current matching and absolute

current accuracy. The absolute accuracy is also determined by

FIGURE 19. MINIMUM DIMMING LINEARITY AT 200Hz

FIGURE 20. MINIMUM DIMMING LINEARITY AT 20kHz

30

25

20

15

10

6

7

8

9

1011

121314

PWM DIMMING DUTY CYCLE (%)

NO CH CAPS

0 0.4

1.2

2.0

2.8 3.2 3.6

4.4 4.8

0.8

1.6

2.4

4.0

5.2

1.2

1.0

0.8

0.6

0.4

0.2

0.0

PWM DIMMING DUTY CYCLE (%)

FIGURE 21. SIMPLIFIED CURRENT SOURCE CIRCUIT

REF

+

-

+

-

PWM DIMMING

RSET

+

REF

+

-

+

-

RSET

-