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33FJ64GP310 Datasheet(PDF) 8 Page - Microchip Technology |
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33FJ64GP310 Datasheet(HTML) 8 Page - Microchip Technology |
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8 / 90 page  dsPIC33F DS70155C-page 6 Preliminary © 2005 Microchip Technology Inc. 2.0 dsPIC33F DEVICE FAMILY OVERVIEW The dsPIC33F device family employs a powerful 16-bit architecture that seamlessly integrates the control features of a Microcontroller (MCU) with the computational capabilities of a Digital Signal Processor (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive computations, as well as control. The DSP engine, dual 40-bit accumulators, hardware support for division operations, barrel shifter, 17 x 17 multiplier, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the dsPIC33F Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the dsPIC33F devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use dsPIC33F devices. Figure 2-1 shows a sample device block diagram typical of the dsPIC33F product family. FIGURE 2-1: dsPIC33F DEVICE BLOCK DIAGRAM Barrel Shifter ACCA<40> ACCB<40> DSP Engine Divide Control 17 x 17 Multiplier W Register Array 16 x 16 Memory Mapped 16-bit ALU Program Flash Memory Data Access Y AGU X AGU Program Counter <23 bits> Instruction Prefetch & Decode X-Data Bus <16-bit> Y-Data Bus <16-bit> Data SRAM up to 28 Kbytes Flash Program Memory up to 256 Kbytes Peripherals I/O Ports 24 23 Legend: MCU/DSP X-Data Path DSP Y-Data Path Address Path Status Register Dual Port RAM 2 Kbytes DMA Controller |
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