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AD7863BR-10REEL Datasheet(PDF) 7 Page - Analog Devices |
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AD7863BR-10REEL Datasheet(HTML) 7 Page - Analog Devices |
7 / 24 page AD7863 Rev. B | Page 7 of 24 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB1 DB2 DB3 DB4 DB5 DB6 CONVST DB12 DB11 DB10 DB9 DGND DB7 DB8 VA2 VREF A0 CS DB13 AGND VB1 VA1 RD BUSY VDD VB2 AGND DB0 AD7863 TOP VIEW (Not to Scale) Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. Mnemonic Description 1 to 6 DB12 to DB7 Data Bit 12 to Data Bit 7. Three-state TTL outputs. 7 DGND Digital Ground. Ground reference for digital circuitry. 8 CONVST Convert Start Input. Logic input. A high-to-low transition on this input puts both track/holds into their hold mode and starts conversion on both channels. 9 to 15 DB6 to DB0 Data Bit 6 to Data Bit 0. Three-state TTL outputs. 16 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 17 VB2 Input Number 2 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 18 VA2 Input Number 2 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 19 VREF Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the output reference source for the analog-to-digital converter. The nominal reference voltage is 2.5 V, and this appears at the pin. 20 A0 Multiplexer Select. This input is used in conjunction with CONVST to determine on which pair of channels the conversion is to be performed. If A0 is low when the conversion is initiated, then channels VA1 and VA2 are selected. If A0 is high when the conversion is initiated, channels VB1 and VB2 are selected. 21 CS Chip Select Input. Active low logic input. The device is selected when this input is active. 22 RD Read Input. Active low logic input. This input is used in conjunction with CS low to enable the data outputs and read a conversion result from the AD7863. 23 BUSY Busy Output. The busy output is triggered high by the falling edge of CONVST and remains high until conversion is completed. 24 VDD Analog and Digital Positive Supply Voltage, 5.0 V ± 5%. 25 VA1 Input Number 1 of Channel A. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 26 VB1 Input Number 1 of Channel B. Analog input voltage ranges of ±10 V (AD7863-10), ±2.5 V (AD7863-3), and 0 V to 2.5 V (AD7863-2). 27 AGND Analog Ground. Ground reference for mux, track/hold, reference, and DAC circuitry. 28 DB13 Data Bit 13 (MSB). Three-state TTL output. Output coding is twos complement for the AD7863-10 and AD7863-3. Output coding is straight (natural) binary for the AD7863-2. |
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